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Implementation of the DMA logic up to 2/12/24.  [Note: Testbench creation and full_DMA signal mapping is pending]
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kkoloth 2024-12-02 21:51:14 +01:00
commit 91dbf4503c
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92
DMA_CONTROLLER.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------DMA Controller Entity---------------------------
entity DMA_Controller is
port(
clk : in std_logic;
rst : in std_logic;
rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc
Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc
Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core
Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM
Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM
Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC
Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core
);
end entity;
----------------------DMA Controller Behaviour------------------------
architecture DMA_Controller_Arch of DMA_Controller is
Signal Count_from_NoC : std_logic_vector(4 downto 0);
Signal Count_to_NoC : std_logic_vector(4 downto 0);
Signal Address_to_RAM : std_logic_vector(6 downto 0);
begin
process(clk, rst)
begin
if rst = '0' then
Sent_valid_from_DMA_to_NoC <= '0';
Address_bus_From_DMA <= (others => '0');
Read_write_Enable_From_DMA <= (others => '0');
tx_packet_length_noc_From_DMA <= (others => '0');
Data_trans_from_DMA_to_core <= (others => '0');
Count_from_NoC <= (others => '0');
Count_to_NoC <= (others => '0');
Address_to_RAM <= (others => '0');
elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------
if Funct_core_to_DMA = "111 1111" then --- x"7f" is just randomly choosen value <[need to find an funct]>
if Count_from_NoC < Size_core_to_DMA then --comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA
if Count_from_NoC = "00000" then
Address_to_RAM <= Address_core_to_DMA;
end if;
if Receive_valid_to_DMA_from_Noc = '1' then
Address_bus_From_DMA <= Address_to_RAM;
Read_write_Enable_From_DMA <= "01"; --Write Enable
Data_trans_from_DMA_to_core <= Count_from_NoC;
Address_to_RAM <= Address_to_RAM + 1;
Count_from_NoC <= Count_from_NoC + 1;
end if;
end if;
else
Count_from_NoC <= (others => '0');
Read_write_Enable_From_DMA <= (others => '0');
end if;
----------------------Reading from RAM to NOC------------------------
if Funct_core_to_DMA = "111 0000" then --- x"70" is just randomly choosen value <[need to find an funct]>
if Count_to_NoC < Size_core_to_DMA then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc
if Count_to_NoC = "00000" then
Address_to_RAM <= Address_core_to_DMA;
tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit
end if;
Address_bus_From_DMA <= Address_to_RAM;
Read_write_Enable_From_DMA <= "10"; --Write Enable
Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc;
Address_to_RAM <= Address_to_RAM + 1;
Count_to_NoC <= Count_to_NoC + 1;
Sent_valid_from_DMA_to_NoC <= '1';
end if;
else
Count_from_NoC <= (others => '0');
Read_write_Enable_From_DMA <= (others => '0');
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------Full DMA Entity---------------------------
entity Full_DMA is
generic (
SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
port(
clk : in std_logic;
rst : in std_logic;
local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc
local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC
local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0);--To NoC
);
end entity;
----------------------Full DMA Behaviour------------------------
architecture Full_DMA_Arch of Full_DMA is
component Single_Port_RAM is
port(
clk : in std_logic;
rst : in std_logic;
Address_bus : in std_logic_vector(7 downto 0); --From DMA
Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA
Data_bus_in : in std_logic_vector(7 downto 0); --From Noc
Data_bus_out : out std_logic_vector(7 downto 0) --From Noc
);
end component;
component Noc_Interface is
generic (
SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
port(
clk : in std_logic;
rst : in std_logic;
Sent_valid_from_DMA : in std_logic; --From DMA
Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA
local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc
local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC
rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA
local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC
local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC
Receive_valid_to_DMA : out std_logic; --To DMA
Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA
Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM
);
end component;
component RoCC_Interface is
port(
clk : in std_logic;
rst : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA
Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA
Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA
);
end component;
component DMA_Controller is
port(
clk : in std_logic;
rst : in std_logic;
rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc
Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc
Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core
Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM
Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM
Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC
Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core
);
end component;
signal Address_bus_sig : std_logic_vector(7 downto 0);
signal Read_write_Enable_sig : std_logic_vector(1 downto 0);
signal Data_bus_in_sig : std_logic_vector(7 downto 0);
signal Data_bus_out_sig : std_logic_vector(7 downto 0);
signal Sent_valid_from_DMA_sig : std_logic;
signal Data_bus_noc_in_sig : std_logic_vector(7 downto 0);
signal tx_packet_length_noc_sig : std_logic_vector(4 downto 0);
signal rx_packet_length_noc_sig : std_logic_vector(4 downto 0);
signal local_noc_tx_sig : std_logic_vector(31 downto 0);
signal local_vc_write_rx_noc_sig : std_logic;
signal Receive_valid_to_DMA_sig : std_logic;
signal Sent_Ack_to_DMA_sig : std_logic_vector(4 downto 0);
signal Data_bus_noc_out_sig : std_logic_vector(7 downto 0);
signal Data_trans_from_DMA_sig : std_logic_vector(4 downto 0);
signal Funct_to_DMA_sig : std_logic_vector(6 downto 0);
signal Address_to_DMA_sig : std_logic_vector(6 downto 0);
signal Size_to_DMA_sig : std_logic_vector(4 downto 0);
signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(4 downto 0);
signal Receive_valid_to_DMA_from_Noc_sig : std_logic;
signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(4 downto 0);
signal Funct_core_to_DMA_sig : std_logic_vector(6 downto 0);
signal Address_core_to_DMA_sig : std_logic_vector(6 downto 0);
Signal Size_core_to_DMA_sig : std_logic_vector(4 downto 0);
signal Address_bus_From_DMA_sig : std_logic_vector(7 downto 0);
signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0);
signal Sent_valid_from_DMA_to_NoC_sig : std_logic;
signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(4 downto 0);
signal Data_trans_from_DMA_to_core_sig : std_logic_vector(4 downto 0);
begin
-- Single_Port_RAM mapping
Single_Port_RAM_inst : Single_Port_RAM
port map(
clk => clk,
rst => rst,
Address_bus => Address_bus_sig,
Read_write_Enable => Read_write_Enable_sig,
Data_bus_in => Data_bus_in_sig, -- Assuming data input comes from NoC
Data_bus_out => Data_bus_out_sig
);
-- Noc_Interface mapping
Noc_Interface_inst : Noc_Interface
generic map (
SOURCE_ID => SOURCE_ID_NEW,
DEST_ID => DEST_ID_NEW
)
port map(
clk => clk,
rst => rst,
Sent_valid_from_DMA => Sent_valid_from_DMA_sig,
Data_bus_noc_in => Data_bus_in_sig,
tx_packet_length_noc => tx_packet_length_noc_sig,
local_noc_rx => local_noc_rx, ---
local_vc_write_tx_noc=> local_vc_write_tx_noc, ---
rx_packet_length_noc => rx_packet_length_noc_sig,
local_noc_tx => local_noc_tx, ---
local_vc_write_rx_noc=> local_vc_write_rx_noc, ---
Receive_valid_to_DMA => Receive_valid_to_DMA_sig,
Sent_Ack_to_DMA => Sent_Ack_to_DMA_sig,
Data_bus_noc_out => Data_bus_out_sig
);
-- RoCC_Interface mapping
RoCC_Interface_inst : RoCC_Interface
port map(
clk => clk,
rst => rst,
cmd_valid => cmd_valid, ---
Cmd_inst_funct => Cmd_inst_funct, ---
Cmd_inst_opcode => Cmd_inst_opcode, ---
Cmd_inst_rd => Cmd_inst_rd, ---
Cmd_inst_rs1 => Cmd_inst_rs1, ---
Cmd_inst_rs2 => Cmd_inst_rs2, ---
Cmd_inst_xd => Cmd_inst_xd, ---
Cmd_inst_xs1 => Cmd_inst_xs1, ---
Cmd_inst_xs2 => Cmd_inst_xs2, ---
Cmd_rs1 => Cmd_rs1, ---
Cmd_rs2 => Cmd_rs2, ---
Data_trans_from_DMA => Data_trans_from_DMA_sig,
Cmd_busy => Cmd_busy, ---
Cmd_ready => Cmd_ready, ---
Funct_to_DMA => Funct_to_DMA_sig,
Address_to_DMA => Address_to_DMA_sig,
Size_to_DMA => Size_to_DMA_sig
);
-- DMA_Controller mapping
DMA_Controller_inst : DMA_Controller
port map(
clk => clk,
rst => rst,
rx_packet_length_noc_to_DMA => rx_packet_length_noc_to_DMA_sig,
Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_from_Noc_sig,
Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_from_Noc_sig,
Funct_core_to_DMA => Funct_core_to_DMA_sig,
Address_core_to_DMA => Address_core_to_DMA_sig,
Size_core_to_DMA => Size_core_to_DMA_sig,
Address_bus_From_DMA => Address_bus_From_DMA_sig,
Read_write_Enable_From_DMA => Read_write_Enable_From_DMA_sig,
Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_to_NoC_sig,
tx_packet_length_noc_From_DMA => tx_packet_length_noc_From_DMA_sig,
Data_trans_from_DMA_to_core => Data_trans_from_DMA_to_core_sig
);
----mapping need to be done yet-------------

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-- Header structure:
-----------------------------------------------------------------------------------------------------
--| | | 2bit | 2bit | 2bit | 2bit | 2bit | 2bit | |
--| Flit_padding | Packet_id | Z_src | Y_src | X_src | Z_dest | Y_dest | X_dest | Packet_length |
--|31 3bits 29|28 12 bits 17|16 6bits 11|10 6bits 5|4 5bits 0|
-----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------NoC Interface Entity---------------------------
entity Noc_Interface is
generic (
SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
port(
clk : in std_logic;
rst : in std_logic;
Sent_valid_from_DMA : in std_logic; --From DMA
Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA
local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc
local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC
rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA
local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC
local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC
Receive_valid_to_DMA : out std_logic; --To DMA
Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA
Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM
);
end entity;
----------------------NoC Interface Behaviour------------------------
architecture Noc_Interface_Arch of Noc_Interface is
Signal packet_id : std_logic_vector(11 downto 0);
signal count : std_logic_vector(4 downto 0);
signal Sent_packet : std_logic_vector(4 downto 0);
--signal packet_length : std_logic_vector(4 downto 0);
begin
rxprocess : process(clk, rst)
begin
if rst = '0' then
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_rx_noc <= (others => '0');
Receive_valid_to_DMA <= (others => '0');
Sent_Ack_to_DMA <= (others => '0');
Data_bus_noc_out <= (others => '0');
count <= (others => '0');
Sent_packet <= (others => '0');
packet_id <= (others => '0');
elsif rising_edge(clk) then
--------------------Reading from NoC--------------------------------
if (local_vc_write_tx_noc = '1') then
if (local_vc_write_tx_noc(31 downto 29) = "100") then
rx_packet_length_noc <= local_vc_write_tx_noc(4 downto 0 ); --packet length
count <= (others => '0'); --counter reset
packet_id <= local_vc_write_tx_noc(28 downto 17); --current packetid
elsif(count < local_vc_write_tx_noc(4 downto 0 )) then
Receive_valid_to_DMA <= '1'; --valid to DMA
count <= count + 1; --counter update
Data_bus_noc_out <= local_vc_write_tx_noc(7 downto 0 ); --NoC is given to RAM
else
Receive_valid_to_DMA <= '0';
Data_bus_noc_out <= (others=>'0');
count <= (others=>'0');
end if;
--------------------Writing to NoC----------------------------------
elsif (Sent_valid_from_DMA = '1' and tx_packet_length_noc > 0) then
if(Sent_packet = "00000") then
Sent_Ack_to_DMA <= Sent_packet + 1; --to DMA updated value
Sent_packet <= Sent_packet + 1;
--updating packet id
local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc;
local_vc_write_rx_noc <= '1';
else
Sent_Ack_to_DMA <= Sent_packet + 1; --to DMA updated value
Sent_packet <= Sent_packet + 1;
local_noc_tx <= (others => '0') & Data_bus_noc_in;; --24bit zeros in msb and 8 bit data
local_vc_write_rx_noc <= '1';
end if;
else
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_rx_noc <= (others => '0');
Receive_valid_to_DMA <= (others => '0');
Sent_Ack_to_DMA <= (others => '0');
Data_bus_noc_out <= (others => '0');
count <= (others => '0');
Sent_packet <= (others => '0');
end if;
end if;
end process;
end architecture;

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-- Execute custom RISC-V instructions structure:
----------------------------------------------------------------------------------------
--| 7bits | 5bits | 6bits | 1bit | 1bit | 1bit | 5bit | 7bit |
--| Funct | rs2 | rs1 | xd | xs1 | xs2 | rd | opcode |
--|31 25|24 20|19 15| 14 | 13 | 12 |11 7|6 0|
----------------------------------------------------------------------------------------
--ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) variables avaliable for baremetalC is rs1,rs2-register address and funct-function
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------RoCC Interface Entity---------------------------
entity RoCC_Interface is
port(
clk : in std_logic;
rst : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA
Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA
Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA
);
end entity;
----------------------Rocc Interface Behaviour------------------------
architecture Noc_Interface_Arch of Noc_Interface is
Signal Cmd_rs1_sig : std_logic_vector(63 downto 0);
signal Cmd_rs1_sig : std_logic_vector(63 downto 0);
Signal Cmd_inst_funct_sig : std_logic_vector(6 downto 0);
Signal cmd_valid_sig : std_logic;
--signal Sent_packet : std_logic_vector(4 downto 0);
--signal packet_length : std_logic_vector(4 downto 0);
begin
process(clk, rst)
begin
if rst = '0' then
Cmd_busy <= '0';
Cmd_ready <= '1'; --To Core --always one
cmd_valid_sig <= '0';
Funct_to_DMA <= (others => '0');
Address_to_DMA <= (others => '0');
Size_to_DMA <= (others => '0');
Cmd_rs1_sig <= (others => '0');
Cmd_rs1_sig <= (others => '0');
Cmd_inst_funct_sig <= (others => '0');
elsif rising_edge(clk) then
--------------------Reading from RoCC--------------------------------
if (cmd_valid = '1') then
Cmd_rs1_sig <= Cmd_rs1;
Cmd_rs2_sig <= Cmd_rs2; --size 4 downto 0 [5bits]
Cmd_inst_funct_sig <= Cmd_inst_funct;
cmd_valid_sig <= '1';
end if;
--------------------Send to the DMA--------------------------------
if(cmd_valid_sig = '1' and Cmd_rs2_sig(4 downto 0) > Data_trans_from_DMA) then
Funct_to_DMA <= Cmd_inst_funct_sig;
Address_to_DMA <= Cmd_rs1_sig(6 downto 0);
Size_to_DMA <= Cmd_rs2_sig(4 downto 0);
else
cmd_valid_sig <= '0';
Cmd_rs1_sig <= (others => '0');
Cmd_rs1_sig <= (others => '0');
Cmd_inst_funct_sig <= (others => '0');
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------RAM Entity---------------------------
entity Single_Port_RAM is
port(
clk : in std_logic;
rst : in std_logic;
Address_bus : in std_logic_vector(7 downto 0); --From DMA
Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA
Data_bus_in : in std_logic_vector(7 downto 0); --From Noc
Data_bus_out : out std_logic_vector(7 downto 0) --From Noc
);
end entity;
----------------------RAM Behaviour------------------------
architecture Single_Port_RAM_behav of Single_Port_RAM is
------- define the new type for the 128x8 RAM
type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0);
-------- initial values in the RAM to X00
signal RAM: RAM_ARRAY := (others=>x"00");
signal initialized : std_logic; -- Initialization flag
begin
process(clk, rst)
begin
if rst = '0' then -- inverted reset
Data_bus_out <= (others => '0');
initialized <= '1';
elsif rising_edge(clk) then
--Setting value to the RAM to coresponding index
if initialized = '1' then
for i in 0 to 127 loop
RAM(i) <= std_logic_vector(to_unsigned(i,8));
end loop;
initialized <= '0';
end if;
--Read Write functionality of RAM
if (Read_write_Enable(0) = '0' and Read_write_Enable(1) = '1' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
Data_bus_out <= RAM(to_integer(unsigned(Address_bus(6 downto 0 )))); -- read data from RAM
elsif (Read_write_Enable(0) = '1' and Read_write_Enable(1) = '0') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
RAM(to_integer(unsigned(Address_bus(6 downto 0)))) <= Data_bus_in(7 downto 0); -- Write data to RAM
Data_bus_out <= (others => '0');
else
Data_bus_out <= (others => '0');
end if;
end if;
end process;
end architecture;