kkoloth/DMA_for_RoCC
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

updating the dma with full_noc support

Browse source
This commit is contained in:
root 2024-12-16 23:26:48 +01:00
parent b33a003706
commit db822d681c
41 changed files with 9714 additions and 450 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

158
DMA_CONTROLLER.vhd
View file

@ -3,123 +3,125 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------DMA Controller Entity---------------------------
entity DMA_Controller is
entity dma_controller is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
-- constant ID_SIZE : integer := 4; -- Define constant for vector size for size of Id's 5 bits
generic (
DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
ID_SIZE : integer := 4 -- Define constant for vector size for size of Id's 5 bits
RAM_WRITE_CMD : natural := 15; -- Writing to ram command from rocc
RAM_READ_CMD : natural := 127; -- Reading from ram command from rocc
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
ADDRESS_SIZE : natural := 6; -- Define constant for vector size for address 7 bits
ID_SIZE : natural := 4 -- Define constant for vector size for size of Id's 5 bits
);
port(
clk : in std_logic;
rst : in std_logic;
rx_packet_length_noc_to_DMA : in std_logic_vector(ID_SIZE downto 0); --To DMA From Noc
Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
Sent_Ack_to_DMA_from_Noc : in std_logic_vector(ID_SIZE downto 0);--------To DMA From Noc
Funct_core_to_DMA : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core
Address_core_to_DMA : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core
Size_core_to_DMA : in std_logic_vector(ID_SIZE downto 0); --To DMA From Core
Address_bus_From_DMA : out std_logic_vector(ADDRESS_SIZE downto 0); --From DMA To RAM
Read_Enable_From_DMA : out std_logic; --From DMA To RAM
Write_Enable_From_DMA : out std_logic; --From DMA To RAM
Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
tx_packet_length_noc_From_DMA : out std_logic_vector(ID_SIZE downto 0); --From DMA To NoC
Data_trans_from_DMA_to_core : out std_logic_vector(ID_SIZE downto 0) --From DMA To Core
rx_packet_length_noc_to_dma : in std_logic_vector(ID_SIZE downto 0); --To DMA From Noc
receive_valid_to_dma_from_noc : in std_logic; --To DMA From Noc
sent_ack_to_dma_from_noc : in std_logic_vector(ID_SIZE downto 0);--------To DMA From Noc
funct_core_to_dma : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core
address_core_to_dma : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core
size_core_to_dma : in std_logic_vector(ID_SIZE downto 0); --To DMA From Core
address_bus_from_dma : out std_logic_vector(ADDRESS_SIZE downto 0); --From DMA To RAM
read_enable_from_dma : out std_logic; --From DMA To RAM
write_enable_from_dma : out std_logic; --From DMA To RAM
sent_valid_from_dma_to_noc : out std_logic; --From DMA To NoC
tx_packet_length_noc_from_dma : out std_logic_vector(ID_SIZE downto 0); --From DMA To NoC
data_trans_from_dma_to_core : out std_logic_vector(ID_SIZE downto 0) --From DMA To Core
);
end entity;
----------------------DMA Controller Behaviour------------------------
architecture DMA_Controller_Arch of DMA_Controller is
Signal Count_from_NoC : std_logic_vector(ID_SIZE downto 0);
Signal Count_to_NoC : std_logic_vector(ID_SIZE downto 0);
Signal Address_to_RAM : std_logic_vector(ADDRESS_SIZE downto 0);
architecture dma_controller_arch of dma_controller is
--Signal count_from_noc : std_logic_vector(ID_SIZE downto 0);
Signal count_to_noc : std_logic_vector(ID_SIZE downto 0);
Signal address_to_ram : std_logic_vector(ADDRESS_SIZE downto 0);
begin
process(clk, rst)
begin
if rst = '0' then
Sent_valid_from_DMA_to_NoC <= '0';
Read_Enable_From_DMA <= '0';
Write_Enable_From_DMA <= '0';
Address_bus_From_DMA <= (others => '0');
tx_packet_length_noc_From_DMA <= (others => '0');
Data_trans_from_DMA_to_core <= (others => '0');
Count_from_NoC <= (others => '0');
Count_to_NoC <= (others => '0');
Address_to_RAM <= (others => '0');
sent_valid_from_dma_to_noc <= '0';
read_enable_from_dma <= '0';
write_enable_from_dma <= '0';
address_bus_from_dma <= (others => '0');
tx_packet_length_noc_from_dma <= (others => '0');
data_trans_from_dma_to_core <= (others => '0');
-- count_from_noc <= (others => '0');
count_to_noc <= (others => '0');
address_to_ram <= (others => '0');
elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------
if Funct_core_to_DMA = std_logic_vector(to_unsigned(15, 7)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface
if unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA
if Count_to_NoC = "00000" then ---count_from_Noc but not working in the wave simulation
Address_to_RAM <= Address_core_to_DMA;
Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1);
--Write_Enable_From_DMA <= '1'; --Write Enable
if funct_core_to_dma = std_logic_vector(to_unsigned(RAM_WRITE_CMD, DATA_SIZE)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface
if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_dma = size_core_to_dma
if count_to_noc = "00000" then ---count_from_noc but not working in the wave simulation
address_to_ram <= address_core_to_dma;
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
--write_enable_from_dma <= '1'; --Write Enable
--end if;
elsif Receive_valid_to_DMA_from_Noc = '1' then
Address_bus_From_DMA <= Address_to_RAM;
--report "Write_Enable_From_DMA is 1 from Line 68";
Write_Enable_From_DMA <= '1'; --Write Enable ----<<<<Why the value is not updateded>>>>
Read_Enable_From_DMA <= '0'; --'0'
Data_trans_from_DMA_to_core <= Count_to_NoC ;-- std_logic_vector(unsigned(Count_to_NoC) - 1)
Address_to_RAM <= std_logic_vector(unsigned(Address_to_RAM) + 1);
Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1);
elsif receive_valid_to_dma_from_noc = '1' then
address_bus_from_dma <= address_to_ram;
--report "write_enable_from_dma is 1 from Line 68";
write_enable_from_dma <= '1'; --Write Enable ----<<<<Why the value is not updateded>>>>
read_enable_from_dma <= '0'; --'0'
data_trans_from_dma_to_core <= count_to_noc ;-- std_logic_vector(unsigned(count_to_noc) - 1)
address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
else
----report "Write_Enable_From_DMA is 0 from Line 75";
Write_Enable_From_DMA <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
Read_Enable_From_DMA <= '0'; --'0'
----report "write_enable_from_dma is 0 from Line 75";
write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
read_enable_from_dma <= '0'; --'0'
end if;
else
----report "Write_Enable_From_DMA is 0 from Line 75";
Write_Enable_From_DMA <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
Read_Enable_From_DMA <= '0'; --'0'
----report "write_enable_from_dma is 0 from Line 75";
write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
read_enable_from_dma <= '0'; --'0'
end if;
-- else
-- Count_from_NoC <= (others => '0');
-- Read_Enable_From_DMA <= '0';
-- Write_Enable_From_DMA <= 'Z';--'0';
-- Sent_valid_from_DMA_to_NoC <= '0';
-- count_from_noc <= (others => '0');
-- read_enable_from_dma <= '0';
-- write_enable_from_dma <= 'Z';--'0';
-- sent_valid_from_dma_to_noc <= '0';
-- end if;
----------------------Reading from RAM to NOC------------------------
elsif Funct_core_to_DMA = std_logic_vector(to_unsigned(127, 7)) then --- x"7f" 127 Its arbitarly choosen from RoCC_Interface
if unsigned(Count_to_NoC) < unsigned(Size_core_to_DMA) then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc
if Count_to_NoC = "00000" then
Address_to_RAM <= Address_core_to_DMA;
tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit
Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1);
---Sent_valid_from_DMA_to_NoC <= '1';
elsif funct_core_to_dma = std_logic_vector(to_unsigned(RAM_READ_CMD, DATA_SIZE)) then --- x"7f" 127 Its arbitarly choosen from RoCC_Interface
if unsigned(count_to_noc) < unsigned(size_core_to_dma) then --sent_ack_to_dma_from_noc could be used instead of the count to Noc
if count_to_noc = "00000" then
address_to_ram <= address_core_to_dma;
tx_packet_length_noc_from_dma <= size_core_to_dma; --giving the size to the header of the NoC flit
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
---sent_valid_from_dma_to_noc <= '1';
else
Address_bus_From_DMA <= Address_to_RAM;
Write_Enable_From_DMA <= '0';
Read_Enable_From_DMA <= '1'; --Read Enable
Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc;
Address_to_RAM <= std_logic_vector(unsigned(Address_to_RAM) + 1);
Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1);
Sent_valid_from_DMA_to_NoC <= '1';
address_bus_from_dma <= address_to_ram;
write_enable_from_dma <= '0';
read_enable_from_dma <= '1'; --Read Enable
data_trans_from_dma_to_core <= sent_ack_to_dma_from_noc;
address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
sent_valid_from_dma_to_noc <= '1';
end if;
elsif unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)+2) then
Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1);
Sent_valid_from_DMA_to_NoC <= '1';
elsif unsigned(count_to_noc) < (unsigned(size_core_to_dma)+2) then
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
sent_valid_from_dma_to_noc <= '1';
else
Read_Enable_From_DMA <= '0';
Write_Enable_From_DMA <= '0';
Sent_valid_from_DMA_to_NoC <= '0';
read_enable_from_dma <= '0';
write_enable_from_dma <= '0';
sent_valid_from_dma_to_noc <= '0';
end if;
else
Count_to_NoC <= (others => '0');
Read_Enable_From_DMA <= '0';
--report "Write_Enable_From_DMA is 0 from Line 111";
Write_Enable_From_DMA <= '0';
Sent_valid_from_DMA_to_NoC <= '0';
count_to_noc <= (others => '0');
read_enable_from_dma <= '0';
--report "write_enable_from_dma is 0 from Line 111";
write_enable_from_dma <= '0';
sent_valid_from_dma_to_noc <= '0';
end if;
end if;
end process;

338
FULL_DMA.vhd
View file

@ -3,18 +3,18 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------Full DMA Entity---------------------------
entity Full_DMA is
entity full_dma is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
generic (
DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
@ -22,41 +22,42 @@ entity Full_DMA is
clk : in std_logic;
rst : in std_logic;
local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_incr_rx_vec_noc : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_xd : in std_logic; --From Core
cmd_inst_xs1 : in std_logic; --From Core
cmd_inst_xs2 : in std_logic; --From Core
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC
local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
local_incr_tx_vec_noc : out std_logic --To NoC
);
end entity;
----------------------Full DMA Behaviour------------------------
architecture Full_DMA_Arch of Full_DMA is
component Single_Port_RAM is
architecture full_dma_arch of full_dma is
component single_port_ram is
port(
clk : in std_logic;
rst : in std_logic;
Address_bus : in std_logic_vector(INST_SIZE downto 0); --From DMA
Read_Enable : in std_logic; --From DMA
Write_Enable : in std_logic; --From DMA
Data_bus_in : in std_logic_vector(DATA_SIZE downto 0); --From Noc
Data_bus_out : out std_logic_vector(DATA_SIZE downto 0) --From Noc
address_bus : in std_logic_vector(INST_SIZE downto 0); --From DMA
read_enable : in std_logic; --From DMA
write_enable : in std_logic; --From DMA
data_bus_in : in std_logic_vector(DATA_SIZE downto 0); --From Noc
data_bus_out : out std_logic_vector(DATA_SIZE downto 0) --From Noc
);
end component;
component Noc_Interface is
component noc_interface is
generic (
SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
@ -64,95 +65,102 @@ architecture Full_DMA_Arch of Full_DMA is
port(
clk : in std_logic;
rst : in std_logic;
Sent_valid_from_DMA : in std_logic; --From DMA
Data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
Receive_valid_to_DMA : out std_logic; --To DMA
Sent_Ack_to_DMA : out std_logic_vector(LENGTH downto 0);---------To DMA
Data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
sent_valid_from_dma : in std_logic; --From DMA
data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc
local_vc_write_rx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
local_incr_rx_vec_noc: in std_logic; --From NoC
rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC
local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
local_incr_tx_vec_noc: out std_logic; --To NoC
receive_valid_to_dma : out std_logic; --To DMA
sent_ack_to_dma : out std_logic_vector(LENGTH downto 0);--------- --To DMA
data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
);
end component;
component RoCC_Interface is
component rocc_interface is
port(
clk : in std_logic;
rst : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
Data_trans_from_DMA : in std_logic_vector(LENGTH downto 0); --From DMA
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
Funct_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA
Address_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA
Size_to_DMA : out std_logic_vector(LENGTH downto 0) --To DMA
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_xd : in std_logic; --From Core
cmd_inst_xs1 : in std_logic; --From Core
cmd_inst_xs2 : in std_logic; --From Core
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
data_trans_from_dma : in std_logic_vector(LENGTH downto 0); --From DMA
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
funct_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
address_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
size_to_dma : out std_logic_vector(LENGTH downto 0) --To DMA
);
end component;
component DMA_Controller is
component dma_controller is
port(
clk : in std_logic;
rst : in std_logic;
rx_packet_length_noc_to_DMA : in std_logic_vector(LENGTH downto 0); --To DMA From Noc
Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
Sent_Ack_to_DMA_from_Noc : in std_logic_vector(LENGTH downto 0);--------To DMA From Noc
Funct_core_to_DMA : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core
Address_core_to_DMA : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core
Size_core_to_DMA : in std_logic_vector(LENGTH downto 0); --To DMA From Core
Address_bus_From_DMA : out std_logic_vector(INST_SIZE downto 0); --From DMA To RAM
Read_Enable_From_DMA : out std_logic; --From DMA To RAM
Write_Enable_From_DMA : out std_logic; --From DMA To RAM
Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
tx_packet_length_noc_From_DMA : out std_logic_vector(LENGTH downto 0); --From DMA To NoC
Data_trans_from_DMA_to_core : out std_logic_vector(LENGTH downto 0) --From DMA To Core
rx_packet_length_noc_to_dma : in std_logic_vector(LENGTH downto 0); --To DMA From Noc
receive_valid_to_dma_from_noc : in std_logic; --To DMA From Noc
sent_ack_to_dma_from_noc : in std_logic_vector(LENGTH downto 0);--------To DMA From Noc
funct_core_to_dma : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core
address_core_to_dma : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core
size_core_to_dma : in std_logic_vector(LENGTH downto 0); --To DMA From Core
address_bus_from_dma : out std_logic_vector(INST_SIZE downto 0); --From DMA To RAM
read_enable_From_DMA : out std_logic; --From DMA To RAM
write_enable_from_dma : out std_logic; --From DMA To RAM
sent_valid_from_dma_to_noc : out std_logic; --From DMA To NoC
tx_packet_length_noc_from_dma : out std_logic_vector(LENGTH downto 0); --From DMA To NoC
data_trans_from_dma_to_core : out std_logic_vector(LENGTH downto 0) --From DMA To Core
);
end component;
signal Address_bus_sig : std_logic_vector(INST_SIZE downto 0);
signal Read_Enable_sig : std_logic;
signal Write_Enable_sig : std_logic;
-- signal Read_write_Enable_sig : std_logic_vector(1 downto 0);
signal Data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal Data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
signal address_bus_sig : std_logic_vector(INST_SIZE downto 0);
signal read_enable_sig : std_logic;
signal write_enable_sig : std_logic;
-- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
signal Sent_valid_from_DMA_sig : std_logic;
--signal Data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal sent_valid_from_dma_sig : std_logic;
--signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
--signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
--signal local_vc_write_rx_noc_sig : std_logic;
signal Receive_valid_to_DMA_sig : std_logic;
signal Sent_Ack_to_DMA_sig : std_logic_vector(LENGTH downto 0);
--signal Data_bus_noc_out_sig : std_logic_vector(DATA_SIZE downto 0);
signal receive_valid_to_dma_sig : std_logic;
signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
signal Data_trans_from_DMA_sig : std_logic_vector(LENGTH downto 0);
signal Funct_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
signal Address_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
signal Size_to_DMA_sig : std_logic_vector(LENGTH downto 0);
signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Receive_valid_to_DMA_from_Noc_sig : std_logic;
--signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(LENGTH downto 0);
--signal Funct_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
--signal Address_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
--Signal Size_core_to_DMA_sig : std_logic_vector(LENGTH downto 0);
--signal Address_bus_From_DMA_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0);
--signal Sent_valid_from_DMA_to_NoC_sig : std_logic;
--signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(LENGTH downto 0);
--signal Data_trans_from_DMA_to_core_sig : std_logic_vector(LENGTH downto 0);
--signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal receive_valid_to_dma_from_noc_sig : std_logic;
--signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
--signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
--signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
--Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
--signal sent_valid_from_dma_to_noc_sig : std_logic;
--signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
--signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);
@ -160,20 +168,20 @@ architecture Full_DMA_Arch of Full_DMA is
begin
-- Single_Port_RAM mapping
Single_Port_RAM_inst : Single_Port_RAM
single_port_ram_inst : single_port_ram
port map(
clk => clk,
rst => rst,
Address_bus => Address_bus_sig,
Read_Enable => Read_Enable_sig,
Write_Enable => Write_Enable_sig,
Data_bus_in => Data_bus_in_sig, -- Assuming data input comes from NoC
Data_bus_out => Data_bus_out_sig
address_bus => address_bus_sig,
read_enable => read_enable_sig,
write_enable => write_enable_sig,
data_bus_in => data_bus_in_sig, -- Assuming data input comes from NoC
data_bus_out => data_bus_out_sig
);
-- Noc_Interface mapping
Noc_Interface_inst : Noc_Interface
noc_interface_inst : noc_interface
generic map (
SOURCE_ID => SOURCE_ID_NEW,
DEST_ID => DEST_ID_NEW
@ -181,60 +189,62 @@ architecture Full_DMA_Arch of Full_DMA is
port map(
clk => clk,
rst => rst,
Sent_valid_from_DMA => Sent_valid_from_DMA_sig,
Data_bus_noc_in => Data_bus_out_sig,
sent_valid_from_dma => sent_valid_from_dma_sig,
data_bus_noc_in => data_bus_out_sig,
tx_packet_length_noc => tx_packet_length_noc_sig,
local_noc_rx => local_noc_rx, ---
local_vc_write_tx_noc=> local_vc_write_tx_noc, ---
local_vc_write_rx_noc=> local_vc_write_rx_noc, ---
local_incr_rx_vec_noc=>local_incr_rx_vec_noc, ---
rx_packet_length_noc => rx_packet_length_noc_sig,
local_noc_tx => local_noc_tx, ---
local_vc_write_rx_noc=> local_vc_write_rx_noc, ---
Receive_valid_to_DMA => Receive_valid_to_DMA_sig,
Sent_Ack_to_DMA => Sent_Ack_to_DMA_sig,
Data_bus_noc_out => Data_bus_in_sig
local_vc_write_tx_noc=> local_vc_write_tx_noc, ---
local_incr_tx_vec_noc=> local_incr_tx_vec_noc, ---
receive_valid_to_dma => receive_valid_to_dma_sig,
sent_ack_to_dma => sent_ack_to_dma_sig,
data_bus_noc_out => data_bus_in_sig
);
-- RoCC_Interface mapping
RoCC_Interface_inst : RoCC_Interface
rocc_interface_inst : rocc_interface
port map(
clk => clk,
rst => rst,
cmd_valid => cmd_valid, ---
Cmd_inst_funct => Cmd_inst_funct, ---
Cmd_inst_opcode => Cmd_inst_opcode, ---
Cmd_inst_rd => Cmd_inst_rd, ---
Cmd_inst_rs1 => Cmd_inst_rs1, ---
Cmd_inst_rs2 => Cmd_inst_rs2, ---
Cmd_inst_xd => Cmd_inst_xd, ---
Cmd_inst_xs1 => Cmd_inst_xs1, ---
Cmd_inst_xs2 => Cmd_inst_xs2, ---
Cmd_rs1 => Cmd_rs1, ---
Cmd_rs2 => Cmd_rs2, ---
Data_trans_from_DMA => Data_trans_from_DMA_sig,
Cmd_busy => Cmd_busy, ---
Cmd_ready => Cmd_ready, ---
Funct_to_DMA => Funct_to_DMA_sig,
Address_to_DMA => Address_to_DMA_sig,
Size_to_DMA => Size_to_DMA_sig
cmd_inst_funct => cmd_inst_funct, ---
cmd_inst_opcode => cmd_inst_opcode, ---
cmd_inst_rd => cmd_inst_rd, ---
cmd_inst_rs1 => cmd_inst_rs1, ---
cmd_inst_rs2 => cmd_inst_rs2, ---
cmd_inst_xd => cmd_inst_xd, ---
cmd_inst_xs1 => cmd_inst_xs1, ---
cmd_inst_xs2 => cmd_inst_xs2, ---
cmd_rs1 => cmd_rs1, ---
cmd_rs2 => cmd_rs2, ---
data_trans_from_dma => data_trans_from_dma_sig,
cmd_busy => cmd_busy, ---
cmd_ready => cmd_ready, ---
funct_to_dma => funct_to_dma_sig,
address_to_dma => address_to_dma_sig,
size_to_dma => size_to_dma_sig
);
-- DMA_Controller mapping
DMA_Controller_inst : DMA_Controller
dma_controller_inst : dma_controller
port map(
clk => clk,
rst => rst,
rx_packet_length_noc_to_DMA => rx_packet_length_noc_sig,
Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_sig,
Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_sig,
Funct_core_to_DMA => Funct_to_DMA_sig,
Address_core_to_DMA => Address_to_DMA_sig,
Size_core_to_DMA => Size_to_DMA_sig,
Address_bus_From_DMA => Address_bus_sig,
Read_Enable_From_DMA => Read_Enable_sig,
Write_Enable_From_DMA => Write_Enable_sig,
Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_sig,
tx_packet_length_noc_From_DMA => tx_packet_length_noc_sig,
Data_trans_from_DMA_to_core => Data_trans_from_DMA_sig
rx_packet_length_noc_to_dma => rx_packet_length_noc_sig,
receive_valid_to_dma_from_noc => receive_valid_to_dma_sig,
sent_ack_to_dma_from_noc => sent_ack_to_dma_sig,
funct_core_to_dma => funct_to_dma_sig,
address_core_to_dma => address_to_dma_sig,
size_core_to_dma => size_to_dma_sig,
address_bus_from_dma => address_bus_sig,
read_enable_From_DMA => read_enable_sig,
write_enable_from_dma => write_enable_sig,
sent_valid_from_dma_to_noc => sent_valid_from_dma_sig,
tx_packet_length_noc_from_dma => tx_packet_length_noc_sig,
data_trans_from_dma_to_core => data_trans_from_dma_sig
);
@ -244,35 +254,35 @@ end architecture;
-- signal Address_bus_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_Enable_sig : std_logic_vector(1 downto 0);
-- signal Data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal address_bus_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
-- signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Sent_valid_from_DMA_sig : std_logic;
-- signal Data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal sent_valid_from_dma_sig : std_logic;
-- signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
-- signal local_vc_write_rx_noc_sig : std_logic;
-- signal Receive_valid_to_DMA_sig : std_logic;
-- signal Sent_Ack_to_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Data_bus_noc_out_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal receive_valid_to_dma_sig : std_logic;
-- signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Data_trans_from_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Funct_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
-- signal Address_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
-- signal Size_to_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Receive_valid_to_DMA_from_Noc_sig : std_logic;
-- signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(LENGTH downto 0);
-- signal Funct_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
-- signal Address_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0);
-- Signal Size_core_to_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Address_bus_From_DMA_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0);
-- signal Sent_valid_from_DMA_to_NoC_sig : std_logic;
-- signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(LENGTH downto 0);
-- signal Data_trans_from_DMA_to_core_sig : std_logic_vector(LENGTH downto 0);
-- signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal receive_valid_to_dma_from_noc_sig : std_logic;
-- signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
-- signal sent_valid_from_dma_to_noc_sig : std_logic;
-- signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);

331
FULL_DMA_tb.vhd
View file

@ -1,23 +1,36 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
-- vcom -work work -2008 -explicit -stats=none D:/project_item_ids/DMA_VHDL/DMA_ARCH_MODULAR_DESGIN/FULL_DMA_tb.vhd
---vsim -gui work.fulldmatb
entity fulldmaTB is
entity fulldmatb is
end entity;
architecture fulldmaTB_arch of fulldmaTB is
constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
component Full_DMA is
architecture fulldmatb_arch of fulldmatb is
constant DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
constant INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
constant DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(15, 7)); --"0001111";
constant DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(127, 7)); --"1111111";
-- constant SOURCE_ID_int1 : integer := 1;
-- constant DEST_ID_int1 : integer := 0;
-- constant SOURCE_ID_int2 : integer := 0;
-- constant DEST_ID_int2 : integer := 1;
---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0);
component full_dma is
generic (
DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
@ -25,49 +38,82 @@ architecture fulldmaTB_arch of fulldmaTB is
clk : in std_logic;
rst : in std_logic;
local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_incr_rx_vec_noc : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_xd : in std_logic; --From Core
cmd_inst_xs1 : in std_logic; --From Core
cmd_inst_xs2 : in std_logic; --From Core
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC
local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
local_incr_tx_vec_noc : out std_logic --To NoC
);
end component;
component full_noc is
port(
clk, rst : in std_logic;
local_rx : in flit_vector(48-1 downto 0);
local_vc_write_rx : in std_logic_vector(192-1 downto 0);
local_incr_rx_vec : in std_logic_vector(192-1 downto 0);
local_tx : out flit_vector(48-1 downto 0);
local_vc_write_tx : out std_logic_vector(192-1 downto 0);
local_incr_tx_vec : out std_logic_vector(192-1 downto 0)
);
end component;
signal clk_tb : std_logic;
signal rst_tb : std_logic;
signal local_noc_rx1, local_noc_rx2 : std_logic_vector(PACKET downto 0);
signal local_rx_sig : flit_vector(48-1 downto 0) := (others => (others => '0')); --map coressponding flit to port
signal local_tx_sig : flit_vector(48-1 downto 0) := (others => (others => '0'));
signal local_vc_write_rx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_incr_rx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_vc_write_tx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_incr_tx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_vc_write_tx_noc1 : std_logic;
signal cmd_valid,local_vc_write_tx_noc2 : std_logic;
signal Cmd_inst_funct1,Cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
signal Cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0);
signal Cmd_inst_rd : std_logic_vector(LENGTH downto 0);
signal Cmd_inst_rs1 : std_logic_vector(LENGTH downto 0);
signal Cmd_inst_rs2 : std_logic_vector(LENGTH downto 0);
signal Cmd_inst_xd : std_logic;
signal Cmd_inst_xs1 : std_logic;
signal Cmd_inst_xs2 : std_logic;
signal Cmd_rs1_1, Cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0);
signal Cmd_rs2_1, Cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
signal Cmd_busy : std_logic;
signal Cmd_ready : std_logic;
signal local_noc_tx1, local_noc_tx2 : std_logic_vector(PACKET downto 0);
signal local_vc_write_rx_noc : std_logic;
signal cmd_inst_funct1,cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
signal cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0);
signal cmd_inst_rd : std_logic_vector(LENGTH downto 0);
signal cmd_inst_rs1 : std_logic_vector(LENGTH downto 0);
signal cmd_inst_rs2 : std_logic_vector(LENGTH downto 0);
signal cmd_inst_xd : std_logic;
signal cmd_inst_xs1 : std_logic;
signal cmd_inst_xs2 : std_logic;
signal cmd_rs1_1, cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0);
signal cmd_rs2_1, cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
signal cmd_busy : std_logic;
signal cmd_ready : std_logic;
signal local_tx_sig1, local_tx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
signal local_rx_sig1, local_rx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
signal local_vc_write_rx_sig1, local_vc_write_rx_sig2 : std_logic;
signal local_vc_write_tx_sig1, local_vc_write_tx_sig2 : std_logic;
signal local_incr_tx_vec_sig1, local_incr_tx_vec_sig2 : std_logic;
signal local_incr_rx_vec_sig1, local_incr_rx_vec_sig2 : std_logic;
signal failed_status_test1 : std_logic := '0';
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
alias ram_sig1 is <<signal.fulldma_inst1.single_port_ram_inst.ram: ram_array>>;
alias ram_sig2 is <<signal.fulldma_inst2.single_port_ram_inst.ram: ram_array>>;
-- alias ram_sig1 is fulldma_inst1.single_port_ram_inst.ram : ram_array;
begin
-- Component instantiation with a label
fulldma_inst1 : Full_DMA
fulldma_inst1 : full_dma
generic map (
SOURCE_ID_NEW => "000001", -- Set source ID
DEST_ID_NEW => "000000" -- Set destination ID
@ -75,26 +121,34 @@ begin
port map (
clk => clk_tb,
rst => rst_tb,
local_noc_rx => local_noc_rx1,
local_vc_write_tx_noc => local_vc_write_tx_noc1,
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst1 + 1)),
-- local_noc_rx => local_rx_sig(DEST_ID_inst1),
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst1 + 1)),
local_noc_rx => local_rx_sig1,
local_vc_write_rx_noc => local_vc_write_rx_sig1,
local_incr_rx_vec_noc => local_incr_rx_vec_sig1,
cmd_valid => cmd_valid,
Cmd_inst_funct => Cmd_inst_funct1,
Cmd_inst_opcode => Cmd_inst_opcode,
Cmd_inst_rd => Cmd_inst_rd,
Cmd_inst_rs1 => Cmd_inst_rs1,
Cmd_inst_rs2 => Cmd_inst_rs2,
Cmd_inst_xd => Cmd_inst_xd,
Cmd_inst_xs1 => Cmd_inst_xs1,
Cmd_inst_xs2 => Cmd_inst_xs2,
Cmd_rs1 => Cmd_rs1_1,
Cmd_rs2 => Cmd_rs2_1,
Cmd_busy => Cmd_busy,
Cmd_ready => Cmd_ready,
local_noc_tx => local_noc_tx1,
local_vc_write_rx_noc => local_vc_write_rx_noc
cmd_inst_funct => cmd_inst_funct1,
cmd_inst_opcode => cmd_inst_opcode,
cmd_inst_rd => cmd_inst_rd,
cmd_inst_rs1 => cmd_inst_rs1,
cmd_inst_rs2 => cmd_inst_rs2,
cmd_inst_xd => cmd_inst_xd,
cmd_inst_xs1 => cmd_inst_xs1,
cmd_inst_xs2 => cmd_inst_xs2,
cmd_rs1 => cmd_rs1_1,
cmd_rs2 => cmd_rs2_1,
cmd_busy => cmd_busy,
cmd_ready => cmd_ready,
local_noc_tx => local_tx_sig1,
local_vc_write_tx_noc => local_vc_write_tx_sig1,
local_incr_tx_vec_noc => local_incr_tx_vec_sig1
-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst1 + 1)),
-- local_noc_tx => local_tx_sig(SOURCE_ID_inst1),
-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst1 + 1))
);
-- Component instantiation with a label
fulldma_inst2 : Full_DMA
fulldma_inst2 : full_dma
generic map (
SOURCE_ID_NEW => "000000", -- Set source ID
DEST_ID_NEW => "000001" -- Set destination ID
@ -102,25 +156,46 @@ begin
port map (
clk => clk_tb,
rst => rst_tb,
local_noc_rx => local_noc_rx2,
local_vc_write_tx_noc => local_vc_write_tx_noc2,
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst2 + 1)),
-- local_noc_rx => local_rx_sig(DEST_ID_inst2),
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst2 + 1)),
local_noc_rx => local_rx_sig2,
local_vc_write_rx_noc => local_vc_write_rx_sig2,
local_incr_rx_vec_noc => local_incr_rx_vec_sig2,
cmd_valid => cmd_valid,
Cmd_inst_funct => Cmd_inst_funct2,
Cmd_inst_opcode => Cmd_inst_opcode,
Cmd_inst_rd => Cmd_inst_rd,
Cmd_inst_rs1 => Cmd_inst_rs1,
Cmd_inst_rs2 => Cmd_inst_rs2,
Cmd_inst_xd => Cmd_inst_xd,
Cmd_inst_xs1 => Cmd_inst_xs1,
Cmd_inst_xs2 => Cmd_inst_xs2,
Cmd_rs1 => Cmd_rs1_2,
Cmd_rs2 => Cmd_rs2_2,
Cmd_busy => Cmd_busy,
Cmd_ready => Cmd_ready,
local_noc_tx => local_noc_tx2,
local_vc_write_rx_noc => local_vc_write_rx_noc
cmd_inst_funct => cmd_inst_funct2,
cmd_inst_opcode => cmd_inst_opcode,
cmd_inst_rd => cmd_inst_rd,
cmd_inst_rs1 => cmd_inst_rs1,
cmd_inst_rs2 => cmd_inst_rs2,
cmd_inst_xd => cmd_inst_xd,
cmd_inst_xs1 => cmd_inst_xs1,
cmd_inst_xs2 => cmd_inst_xs2,
cmd_rs1 => cmd_rs1_2,
cmd_rs2 => cmd_rs2_2,
cmd_busy => cmd_busy,
cmd_ready => cmd_ready,
local_noc_tx => local_tx_sig2,
local_vc_write_tx_noc => local_vc_write_tx_sig2,
local_incr_tx_vec_noc => local_incr_tx_vec_sig2
-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst2 + 1)),
-- local_noc_tx => local_tx_sig(SOURCE_ID_inst2),
-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst2 + 1))
);
full_noc_inst1 : full_noc
port map(
clk => clk_tb,
rst => rst_tb,
local_rx => local_rx_sig,
local_vc_write_rx => local_vc_write_rx_sig,
local_incr_rx_vec => local_incr_rx_vec_sig,
local_tx => local_tx_sig,
local_vc_write_tx => local_vc_write_tx_sig,
local_incr_tx_vec => local_incr_tx_vec_sig
);
-- Clock generation process
clk_process: process
begin
@ -128,43 +203,117 @@ begin
clk_tb <= '1'; wait for 5 ns;
end process;
-----------------------NoC connection has to be changed--------------------
local_noc_rx1 <= local_noc_tx2;
local_noc_rx2 <= local_noc_tx1;
-- local_noc_rx1 <= local_noc_tx2;
-- local_noc_rx2 <= local_noc_tx1;
--inst1 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source one[1]
--rx
local_rx_sig(1) <= local_tx_sig1;
local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1;
--local_incr_rx_vec_sig(0) <= local_incr_tx_vec_sig1;
--tx
local_rx_sig1 <= local_tx_sig(1);
local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4);
--local_incr_rx_vec_sig1 <= local_incr_tx_vec_sig(4);
--inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0]
-- rx
local_rx_sig(0) <= local_tx_sig2;
local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2;
--local_incr_rx_vec_sig(4) <= local_incr_tx_vec_sig2;
--tx destination one[1]
local_rx_sig2 <= local_tx_sig(0);
local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0);
--local_incr_rx_vec_sig2 <= local_incr_tx_vec_sig(0);
-- Simulation process to assign values to CtrlCommand
simproc: process
begin
local_vc_write_tx_noc2 <= '0';
-- local_vc_write_tx_noc2 <= '0';
cmd_valid <= '0';
rst_tb <= '0';
wait for 10 ns;
rst_tb <= '1';
wait for 40 ns;
-----------------------------------------------Test1---------------------------------------------------
-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
Cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
Cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
Cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
Cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
Cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
Cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
local_vc_write_tx_noc2 <= '1';
wait for 80 ns;
local_vc_write_tx_noc2 <= '0';
-- local_vc_write_tx_noc2 <= '1';
wait for 180 ns;
-- local_vc_write_tx_noc2 <= '0';
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
exit; -- Exit the loop
end if;
end loop;
wait for 20 ns;
----------------------------------------------Test2------------------------------------------------------
-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
-- local_vc_write_tx_noc2 <= '1';
wait for 180 ns;
-- local_vc_write_tx_noc2 <= '0';
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
exit; -- Exit the loop
end if;
end loop;
wait for 20 ns;
--------------------------------------------------------------------------------------------------------------
if failed_status_test1 = '0' then
report "Test is passed: memory elements are equal starting locations " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1))) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)))
severity note;
end if;
wait for 1000 ns;
-- wait for 1000 ns ;
-- -- wait for 1000 ns ;
end process;
end architecture;

90
NoC_INTERFACE.vhd
View file

@ -10,42 +10,44 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------NoC Interface Entity---------------------------
entity Noc_Interface is
entity noc_interface is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
-- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits
generic (
DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : natural := 11; -- Define constant for vector size for size of Id's 12 bits
REG_SIZE : natural := 31; -- Define constant for vector size for size of Reg 31 bits
SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
);
port(
clk : in std_logic;
rst : in std_logic;
Sent_valid_from_DMA : in std_logic; --From DMA
Data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
sent_valid_from_dma : in std_logic; --From DMA
data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc
local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC
rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
local_vc_write_rx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
local_incr_rx_vec_noc: in std_logic; --From NoC
rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC
local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC
Receive_valid_to_DMA : out std_logic; --To DMA
Sent_Ack_to_DMA : out std_logic_vector(LENGTH downto 0);-----------To DMA
Data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
local_incr_tx_vec_noc: out std_logic; --To NoC
receive_valid_to_dma : out std_logic; --To DMA
sent_ack_to_dma : out std_logic_vector(LENGTH downto 0);--------- --To DMA
data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
);
end entity;
----------------------NoC Interface Behaviour------------------------
architecture Noc_Interface_Arch of Noc_Interface is
architecture noc_interface_arch of noc_interface is
Signal packet_id : std_logic_vector(PACKET downto 0);
signal count : std_logic_vector(LENGTH downto 0);
signal Sent_packet : std_logic_vector(LENGTH downto 0);
signal sent_packet : std_logic_vector(LENGTH downto 0);
signal packet_len : std_logic_vector(LENGTH downto 0);
@ -57,12 +59,13 @@ begin
if rst = '0' then
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_rx_noc <= '0';
Receive_valid_to_DMA <= '0';
Sent_Ack_to_DMA <= (others => '0');
Data_bus_noc_out <= (others => '0');
local_vc_write_tx_noc <= '0';
--local_incr_tx_vec_noc <= '0';
receive_valid_to_dma <= '0';
sent_ack_to_dma <= (others => '0');
data_bus_noc_out <= (others => '0');
count <= (others => '0');
Sent_packet <= (others => '0');
sent_packet <= (others => '0');
packet_id <= (others => '0');
packet_len <= (others => '0');
@ -70,51 +73,52 @@ begin
--------------------Reading from NoC--------------------------------
if (local_vc_write_tx_noc = '1') then
if (local_vc_write_rx_noc = '1') then
if (local_noc_rx(31 downto 29) = "100") then
rx_packet_length_noc <= local_noc_rx(LENGTH downto 0 ); --packet length
packet_len <= local_noc_rx(LENGTH downto 0 ); --packet length
count <= (others => '0'); --counter reset
packet_id <= local_noc_rx(28 downto 17); --current packetid
Receive_valid_to_DMA <= '1';
receive_valid_to_dma <= '1';
elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then
report "Receive_valid_to_DMA is 1 from Line 80";
report "receive_valid_to_dma is 1 from Line 80";
Receive_valid_to_DMA <= '1'; --valid to DMA
receive_valid_to_dma <= '1'; --valid to DMA
count <= std_logic_vector(unsigned(count) + 1); --counter update
Data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM
data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM
else
report "Receive_valid_to_DMA is 0 from Line 86";
report "receive_valid_to_dma is 0 from Line 86";
packet_len <= (others=>'0');
Receive_valid_to_DMA <= '0';
Data_bus_noc_out <= (others=>'0');
receive_valid_to_dma <= '0';
data_bus_noc_out <= (others=>'0');
count <= (others=>'0');
end if;
--------------------Writing to NoC----------------------------------
elsif ((Sent_valid_from_DMA = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind
if(Sent_packet = "00000") then
--Sent_Ack_to_DMA <= std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value
Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1);
elsif ((sent_valid_from_dma = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind
if(sent_packet = "00000") then
--sent_ack_to_dma <= std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
--updating packet id
local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc;
local_vc_write_rx_noc <= '1';
local_vc_write_tx_noc <= '1';
else
Sent_Ack_to_DMA <= Sent_packet;--std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value
Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1);
local_noc_tx <= std_logic_vector(to_unsigned(0, 24)) & Data_bus_noc_in; --24bit zeros in msb and 8 bit data
local_vc_write_rx_noc <= '1';
sent_ack_to_dma <= sent_packet;--std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
local_noc_tx <= std_logic_vector(to_unsigned(0, 24)) & data_bus_noc_in; --24bit zeros in msb and 8 bit data
local_vc_write_tx_noc <= '1';
end if;
else
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_rx_noc <= '0';
Receive_valid_to_DMA <= '0';
Sent_Ack_to_DMA <= (others => '0');
Data_bus_noc_out <= (others => '0');
local_vc_write_tx_noc <= '0';
---local_incr_tx_vec_noc <= '0';
receive_valid_to_dma <= '0';
sent_ack_to_dma <= (others => '0');
data_bus_noc_out <= (others => '0');
count <= (others => '0');
Sent_packet <= (others => '0');
sent_packet <= (others => '0');
end if;
end if;
end process;

98
ROCC_INTERFACE.vhd
View file

@ -10,46 +10,50 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------RoCC Interface Entity---------------------------
entity RoCC_Interface is
entity rocc_interface is
-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 63 bits
generic (
INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
REG_SIZE : integer := 63 -- Define constant for vector size for size of Reg 63 bits
DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := "0001111";
DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := "1111111";
CORE_WRITE_FUNC : natural := 30; -- Write function from the core
CORE_READ_FUNC : natural := 31; -- Read function from the core
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
PACKET : natural := 11; -- Define constant for vector size for size of Id's 12 bits
REG_SIZE : natural := 63 -- Define constant for vector size for size of Reg 63 bits
);
port(
clk : in std_logic;
rst : in std_logic;
cmd_valid : in std_logic; --From Core
Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
Cmd_inst_xd : in std_logic; --From Core
Cmd_inst_xs1 : in std_logic; --From Core
Cmd_inst_xs2 : in std_logic; --From Core
Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
Data_trans_from_DMA : in std_logic_vector(LENGTH downto 0); --From DMA
Cmd_busy : out std_logic; --To Core
Cmd_ready : out std_logic; --To Core --always one
Funct_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA
Address_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA
Size_to_DMA : out std_logic_vector(LENGTH downto 0) --To DMA
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
cmd_inst_xd : in std_logic; --From Core
cmd_inst_xs1 : in std_logic; --From Core
cmd_inst_xs2 : in std_logic; --From Core
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
data_trans_from_dma : in std_logic_vector(LENGTH downto 0); --From DMA
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
funct_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
address_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
size_to_dma : out std_logic_vector(LENGTH downto 0) --To DMA
);
end entity;
----------------------Rocc Interface Behaviour------------------------
architecture RoCC_Interface_Arch of RoCC_Interface is
Signal Cmd_rs1_sig : std_logic_vector(REG_SIZE downto 0);
signal Cmd_rs2_sig : std_logic_vector(REG_SIZE downto 0);
Signal Cmd_inst_funct_sig : std_logic_vector(INST_SIZE downto 0);
architecture rocc_interface_arch of rocc_interface is
Signal cmd_rs1_sig : std_logic_vector(REG_SIZE downto 0);
signal cmd_rs2_sig : std_logic_vector(REG_SIZE downto 0);
Signal cmd_inst_funct_sig : std_logic_vector(INST_SIZE downto 0);
Signal cmd_valid_sig : std_logic;
--signal Sent_packet : std_logic_vector(4 downto 0);
--signal packet_length : std_logic_vector(4 downto 0);
@ -58,42 +62,42 @@ begin
process(clk, rst)
begin
if rst = '0' then
Cmd_busy <= '0';
Cmd_ready <= '1'; --To Core --always one
cmd_busy <= '0';
cmd_ready <= '1'; --To Core --always one
cmd_valid_sig <= '0';
Funct_to_DMA <= (others => '0');
Address_to_DMA <= (others => '0');
Size_to_DMA <= (others => '0');
Cmd_rs1_sig <= (others => '0');
Cmd_rs2_sig <= (others => '0');
Cmd_inst_funct_sig <= (others => '0');
funct_to_dma <= (others => '0');
address_to_dma <= (others => '0');
size_to_dma <= (others => '0');
cmd_rs1_sig <= (others => '0');
cmd_rs2_sig <= (others => '0');
cmd_inst_funct_sig <= (others => '0');
elsif rising_edge(clk) then
--------------------Send to the DMA--------------------------------
if((cmd_valid_sig = '1') and (Cmd_rs2_sig(LENGTH downto 0) > Data_trans_from_DMA)) then
if Cmd_inst_funct = std_logic_vector(to_unsigned(30, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
Funct_to_DMA <= "0001111";
elsif Cmd_inst_funct = std_logic_vector(to_unsigned(31, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
Funct_to_DMA <= "1111111";
if((cmd_valid_sig = '1') and (cmd_rs2_sig(LENGTH downto 0) > data_trans_from_dma)) then
if cmd_inst_funct = std_logic_vector(to_unsigned(CORE_WRITE_FUNC, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
funct_to_dma <= DMA_WRITE_TO_RAM;
elsif cmd_inst_funct = std_logic_vector(to_unsigned(CORE_READ_FUNC, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
funct_to_dma <= DMA_READ_TO_RAM;
else
Funct_to_DMA <= (others => '0');
funct_to_dma <= (others => '0');
end if;
Address_to_DMA <= Cmd_rs1_sig(INST_SIZE downto 0);
Size_to_DMA <= Cmd_rs2_sig(LENGTH downto 0);
address_to_dma <= cmd_rs1_sig(INST_SIZE downto 0);
size_to_dma <= cmd_rs2_sig(LENGTH downto 0);
--------------------Reading from RoCC--------------------------------
elsif (cmd_valid = '1') then
Cmd_rs1_sig <= Cmd_rs1;
Cmd_rs2_sig <= Cmd_rs2; --size 4 downto 0 [5bits]
Cmd_inst_funct_sig <= Cmd_inst_funct;
cmd_rs1_sig <= cmd_rs1;
cmd_rs2_sig <= cmd_rs2; --size 4 downto 0 [5bits]
cmd_inst_funct_sig <= cmd_inst_funct;
cmd_valid_sig <= '1';
else
cmd_valid_sig <= '0';
Cmd_rs1_sig <= (others => '0');
Cmd_rs1_sig <= (others => '0');
Cmd_inst_funct_sig <= (others => '0');
cmd_rs1_sig <= (others => '0');
cmd_rs1_sig <= (others => '0');
cmd_inst_funct_sig <= (others => '0');
end if;
end if;

50
SINGLE_PORT_RAM.vhd
View file

@ -2,58 +2,58 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------RAM Entity---------------------------
entity Single_Port_RAM is
----------------------ram Entity---------------------------
entity single_port_ram is
generic (
DATA_SIZE : integer := 7; -- Default source ID should be changed
ADDRESS_SIZE : integer := 6 -- Default destination ID should be changed
DATA_SIZE : natural := 7; -- Default source ID should be changed
ADDRESS_SIZE : natural := 6 -- Default destination ID should be changed
);
--constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
--constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
port(
clk : in std_logic;
rst : in std_logic;
Address_bus : in std_logic_vector(ADDRESS_SIZE downto 0); -- From DMA
Read_Enable : in std_logic; -- From DMA
Write_Enable : in std_logic; -- From DMA
Data_bus_in : in std_logic_vector(DATA_SIZE downto 0); -- From NoC
Data_bus_out : out std_logic_vector(DATA_SIZE downto 0) -- From NoC
address_bus : in std_logic_vector(ADDRESS_SIZE downto 0); -- From DMA
read_enable : in std_logic; -- From DMA
write_enable : in std_logic; -- From DMA
data_bus_in : in std_logic_vector(DATA_SIZE downto 0); -- From NoC
data_bus_out : out std_logic_vector(DATA_SIZE downto 0) -- From NoC
);
end entity;
----------------------RAM Behaviour------------------------
architecture Single_Port_RAM_behav of Single_Port_RAM is
----------------------ram Behaviour------------------------
architecture single_port_ram_behav of single_port_ram is
------- define the new type for the 128x8 RAM
type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
-------- initial values in the RAM to X00
signal RAM: RAM_ARRAY := (others=>x"00");
------- define the new type for the 128x8 ram
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
-------- initial values in the ram to X00
signal ram: ram_array := (others=>x"00");
signal initialized : std_logic; -- Initialization flag
begin
process(clk, rst)
begin
if rst = '0' then -- inverted reset
Data_bus_out <= (others => '0');
data_bus_out <= (others => '0');
initialized <= '1';
elsif rising_edge(clk) then
--Setting value to the RAM to coresponding index_testing purpouse
--Setting value to the ram to coresponding index_testing purpouse
-- synthesis translate_off
if initialized = '1' then
for i in 0 to 127 loop
RAM(i) <= std_logic_vector(to_unsigned(i,8));
ram(i) <= std_logic_vector(to_unsigned(i,8));
end loop;
initialized <= '0';
end if;
-- synthesis translate_on
--Read Write functionality of RAM
if (Read_Enable = '1' and Write_Enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
Data_bus_out <= RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0 )))); -- read data from RAM
elsif (Read_Enable = '0' and Write_Enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0)))) <= Data_bus_in(DATA_SIZE downto 0); -- Write data to RAM
Data_bus_out <= (others => '0');
--Read Write functionality of ram
if (read_enable = '1' and write_enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
data_bus_out <= ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0 )))); -- read data from ram
elsif (read_enable = '0' and write_enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0)))) <= data_bus_in(DATA_SIZE downto 0); -- Write data to ram
data_bus_out <= (others => '0');
else
Data_bus_out <= (others => '0');
data_bus_out <= (others => '0');
end if;
end if;
end process;

323
noc_files/NOC_3D_PACKAGE.vhd Normal file
View file

@ -0,0 +1,323 @@
-------------------------------------------------------------------------------
-- Title : Package for modular, heterogenous 3D NoC
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : NOC_3D_PACKAGE.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package including the constants, types, function and components
-- required for the modular, heterogenous 3D NoC.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
package NOC_3D_PACKAGE is
--------------------------------------------------------------------------------
---------------------- CONSTANTS -----------------------------------------------
--------------------------------------------------------------------------------
---- The following lines can be edited to change the router architecture
---- With VHDL2008 these should be generic of the package
constant flit_size : positive := 32; -- Flit size in bits
constant max_vc_num : positive := 4; -- Max VCs of an input phy. channel
constant max_vc_num_out : positive := 4; -- Max VCs of an op. channel
constant max_x_dim : positive := 4; -- Max number of routers in X-dim
constant max_y_dim : positive := 4; -- Max number of routers in Y-dim
constant max_Z_dim : positive := 4; -- Max number of routers in Z-dim
constant max_packet_len : positive := 31; -- Max packet_length in flits
-- (ideal is 2^N-1)
constant max_port_num : positive := 7; -- Max number of router port
-- Which port-num belongs to witch port
constant int_local : natural := 0;
constant int_north : natural := 1;
constant int_east : natural := 2;
constant int_south : natural := 3;
constant int_west : natural := 4;
constant int_up : natural := 5;
constant int_down : natural := 6;
-- General contants for the used technology
constant RST_LVL : std_logic := '0'; -- Level to acticate reset ('1' =>
-- active high; '0' => active low)
-- Clock cycle in nano second
constant clk_period : time := 10 ns;
constant delay_constant : time := 300 ps;
-- Derived constants that cannot be edited (there values is calculated later
-- in the body)
constant packet_len_width : positive; -- Header Bits req. for packet-length
constant x_addr_width : positive; -- Header Bits req. for Dest. Addr X
constant y_addr_width : positive; -- Header Bits req. for Dest. Addr Y
constant z_addr_width : positive; -- Header Bits req. for Dest. Addr Z
--------------------------------------------------------------------------------
--------------------- (SUB)TYPES -----------------------------------------------
--------------------------------------------------------------------------------
-- General
type integer_vec is array (natural range <>) of integer;
type integer_array is array (natural range <>, natural range <>) of integer;
-- Flit related
subtype flit is std_logic_vector(flit_size-1 downto 0);
type flit_vector is array (natural range <>) of
std_logic_vector(flit_size-1 downto 0);
-- Virtual channel related
subtype vc_status_vec is std_logic_vector(max_vc_num-1 downto 0);
subtype vc_status_vec_enc is std_logic_vector(
positive(ceil(log2(real(max_vc_num))))-1 downto 0);
type vc_status_array is array (natural range <>) of vc_status_vec;
type vc_status_array_enc is array (natural range <>) of vc_status_vec_enc;
subtype vc_prop_int is integer_vec(0 to max_vc_num-1); -- integer vc
-- propoerties
-- (e.g. depth)
type vc_prop_int_array is array (natural range <>) of vc_prop_int;
-- Full NoC related
-- Head Flit related
type header_inf is record
packet_length : std_logic_vector(positive(ceil(log2(real(max_packet_len+1))))-1 downto 0);
------------------------------- (packet_len_width-1 downto 0)
x_dest : std_logic_vector(positive(ceil(log2(real(max_x_dim))))-1 downto 0);
------------------------------- (x_addr_width-1 downto 0)
y_dest : std_logic_vector(positive(ceil(log2(real(max_y_dim))))-1 downto 0);
------------------------------- (y_addr_width-1 downto 0)
z_dest : std_logic_vector(positive(ceil(log2(real(max_z_dim))))-1 downto 0);
--------------------------------- (z_addr_width-1 downto 0)
end record;
type header_inf_vector is array (natural range <>) of header_inf;
-- Head Flit related
type address_inf is record
x_dest : std_logic_vector(positive(ceil(log2(real(max_x_dim))))-1 downto 0);
------------------------------- (x_addr_width-1 downto 0)
y_dest : std_logic_vector(positive(ceil(log2(real(max_y_dim))))-1 downto 0);
------------------------------- (y_addr_width-1 downto 0)
z_dest : std_logic_vector(positive(ceil(log2(real(max_z_dim))))-1 downto 0);
--------------------------------- (z_addr_width-1 downto 0)
end record;
---------------------------------------------------------------------------------
------------------ FUNCTION-DEC. ------------------------------------------------
---------------------------------------------------------------------------------
-- Bits required to encode x different values
function bit_width(x : positive) return positive;
-- Transfer std_logic_vector (intp. unsigned) to natural integer
function slv2int(x : std_logic_vector) return natural;
-- Transfer "one_hot" to std_logic_vector
function one_hot2slv(x : std_logic_vector) return std_logic_vector;
-- Transfer "one_hot" to natural integer
function one_hot2int(x : std_logic_vector) return natural;
-- Get the req. information from the head_flit
function get_header_inf(x : std_logic_vector) return header_inf;
-- Get the dest. adress from the header information
function extract_address_inf(x : header_inf) return address_inf;
-- Sum all values of an integer array
function int_vec_sum(x : integer_vec) return integer;
-- Upper range
function upper_range(x : integer_vec; i : natural) return natural;
-- Lower range
function lower_range(x : integer_vec; i : natural) return natural;
-- Get the i^th slice of x (slice sized defined by vec)
function slice(x : std_logic_vector;
vec : integer_vec;
i : natural) return std_logic_vector;
-- Return the index of a value in an array
function ret_index(x : integer_vec; i : integer) return integer;
-- Return the maximum value of an array
function ret_max(x : integer_vec) return integer;
end package NOC_3D_PACKAGE;
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
--------------------- BODY -------------------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
package body NOC_3D_PACKAGE is
-----------------------------------------------------------------------------------
------------------- FUNCTION-DEC. -------------------------------------------------
-----------------------------------------------------------------------------------
-- Bits required to encode x different values
function bit_width(x : positive) return positive is
begin
assert (x > 1) report "Encoding for less than two values is not possible"
severity failure;
return positive(ceil(log2(real(x))));
end function;
-- Derived constants using function bit_width
constant packet_len_width : positive := bit_width(max_packet_len+1);
constant x_addr_width : positive := bit_width(max_x_dim);
constant y_addr_width : positive := bit_width(max_y_dim);
constant z_addr_width : positive := bit_width(max_z_dim);
-- Transfer "std_logic_vector" (intp. unsigned) to "natural integer"
function slv2int(x : std_logic_vector) return natural is
begin
return to_integer(unsigned(x));
end function;
-- Transfer "one_hot" to "std_logic_vector"
function one_hot2slv(x : std_logic_vector) return std_logic_vector is
variable var : std_logic_vector(bit_width(x'length)-1 downto 0);
begin
var := (others => '0');
for i in x'range loop
if x(i) = '1' then
-- use "or" to avoid synthesizing a priority decoder
var := var or std_logic_vector(to_unsigned(i, var'length));
end if;
end loop;
return var;
end function;
-- Transfer "one_hot" to natural
function one_hot2int(x : std_logic_vector) return natural is
variable var : unsigned(bit_width(x'length)-1 downto 0);
begin
var := (others => '0');
for i in x'range loop
if x(i) = '1' then
-- use "or" to avoid synthesizing a priority decoder
var := var or to_unsigned(i, var'length);
end if;
end loop;
return to_integer(var);
end function;
-- The following unit has to be change if the header structure is changes.
-- Currently we assume that the LSBs are the packet-length: the next higher bits
-- are the X, Y and then Z address. All higher value bith are currently used by higher
-- layers. Important sofar is that is that the req. header informations
-- (addr, packet_length) are not allowed to take mor then "flit_size" bits.
function get_header_inf(x : std_logic_vector) return header_inf is
variable y : header_inf;
variable offset : integer;
begin
y.packet_length := x(packet_len_width-1 downto 0);
offset := packet_len_width;
y.x_dest := x(x_addr_width+offset-1 downto offset);
offset := offset + x_addr_width;
y.y_dest := x(y_addr_width+offset-1 downto offset);
offset := offset + y_addr_width;
y.z_dest := x(z_addr_width+offset-1 downto offset);
return y;
end function;
-- Get the address information from a header
function extract_address_inf(x : header_inf) return address_inf is
variable y : address_inf;
begin
y.x_dest := x.x_dest;
y.y_dest := x.y_dest;
y.z_dest := x.z_dest;
return y;
end function;
-- Sum of integer array
function int_vec_sum(x : integer_vec) return integer is
variable var : integer;
begin
var := 0;
for i in x'range loop
var := var + x(i);
end loop;
return var;
end function;
-- Uper range
function upper_range(x : integer_vec; i : natural) return natural is
variable var : natural;
begin
var := 0;
for it in 0 to i loop
var := var + x(it);
end loop;
return var-1;
end function;
-- Lower range
function lower_range(x : integer_vec; i : natural) return natural is
variable var : natural;
begin
var := 0;
for it in 0 to i loop
var := var + x(it);
end loop;
return var-x(i);
end function;
-- Slice of vector
function slice(x : std_logic_vector; vec : integer_vec;
i : natural) return std_logic_vector is
begin
return x(upper_range(vec, i) downto lower_range(vec, i));
end function;
-- Return the position in an array
function ret_index(x : integer_vec; i : integer) return integer is
variable result : integer:=-1;
begin
for index in 0 to x'length-1 loop
if x(x'left+index) = i then
result:= index;
end if;
end loop;
if result=-1 then
assert false report "INDEX IS NOT FOUND" severity error;
end if;
return result;
end function;
-- Return the maximum value of an array
function ret_max(x : integer_vec) return integer is
variable max_value : integer:=0;
begin
for index in 0 to x'length-1 loop
if x(x'left+index) > max_value then
max_value := x(x'left+index);
end if;
end loop;
return max_value;
end function;
end package body NOC_3D_PACKAGE;

137
noc_files/TURNS_3D_NOC.vhd Normal file
View file

@ -0,0 +1,137 @@
-------------------------------------------------------------------------------
-- Title : Package used to define the allowed turns in the used routing
-- algorithms
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : TURNS_3D_NOC.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-30
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package with constant boolean arrays, used to determine which
-- I/0 connections are possible in a router, for a given routing.
-- The package can be easily extended to support more routing al-
-- gorithms, which are then automatically considered for logic
-- minimization (exploits forbidden turns) in the synthesis.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use work.NOC_3D_PACKAGE.all;
package TURNS_3D_NOC is
-- Type used to describe all allowed connections in 2D routers
-- First index of the array defines the "from" the second the "to"
type boolean_vector is array(natural range <>) of boolean;
type turn_table_2D is array(4 downto 0) of boolean_vector(4 downto 0);
-- Type used to describe all allowed connections in 3D routers
type turn_table_3D is array(6 downto 0) of boolean_vector(6 downto 0);
function routes_2D (x : string) return turn_table_2D;
function routes_3D (x : string) return turn_table_3D;
end package TURNS_3D_NOC;
package body TURNS_3D_NOC is
function routes_2D(x : string) return turn_table_2D is
variable y : turn_table_2D := (others => (others => false));
begin
if x = "XY" then
-- From and to "local" always possible, except for U turns
for i in 0 to 4 loop
y(i)(int_local) := true;
end loop;
y(int_local)(4 downto 0) := (others => true);
y(int_local)(int_local) := false;
-- Path following (no turns) always possible
y(int_north)(int_south) := true; y(int_south)(int_north) := true;
y(int_east)(int_west) := true; y(int_west)(int_east) := true;
-- Routing specific remainder
y(int_west)(int_north) := true; y(int_west)(int_south) := true;
y(int_east)(int_north) := true; y(int_east)(int_south) := true;
else
assert false report
x & " 2D routing not implemented for crossbar & arbiter opt. Implementing full connectivity"
severity warning;
y := (others => (others => true));
y(int_local)(int_local) := false; y(int_north)(int_north) := false;
y(int_east)(int_east) := false; y(int_south)(int_south) := false;
y(int_west)(int_west) := false;
end if;
return y;
end function;
function routes_3D(x : string) return turn_table_3D is
variable y : turn_table_3D := (others => (others => false));
begin
if (x = "XYZ") or (x = "ZXY") or (x = "DXYU") or (x = "UXYD") then
-- From and to "local" always possible, except for U-turns
for i in 0 to 6 loop
y(i)(int_local) := true;
end loop;
y(int_local)(6 downto 0) := (others => true);
y(int_local)(int_local) := false;
-- Path following (no turns) always possible
y(int_north)(int_south) := true; y(int_south)(int_north) := true;
y(int_east)(int_west) := true; y(int_west)(int_east) := true;
y(int_down)(int_up) := true; y(int_up)(int_down) := true;
-- Routing specific XY
y(int_west)(int_north) := true; y(int_west)(int_south) := true;
y(int_east)(int_north) := true; y(int_east)(int_south) := true;
if (x = "XYZ") then
-- From everywhere to UP and DOWN
for i in 0 to 6 loop
y(i)(int_up) := true;
end loop;
for i in 0 to 6 loop
y(i)(int_down) := true;
end loop;
elsif (x = "ZXY") then
-- From UP and DOWN to everywhere
y(int_up)(6 downto 0) := (others => true);
y(int_down)(6 downto 0) := (others => true);
elsif (x = "DXYU") then
-- From UP to everywhere, From Everywhere to UP
y(int_up)(6 downto 0) := (others => true);
for i in 0 to 6 loop
y(i)(int_up) := true;
end loop;
else -- UXYD
-- From DOWN to everywhere, From everywhere to DOWN
y(int_down)(6 downto 0) := (others => true);
for i in 0 to 6 loop
y(i)(int_down) := true;
end loop;
end if;
else
assert false report
x & " 3D routing not implemented for crossbar & arbiter opt. Implementing full connectivity"
severity warning;
y := (others => (others => true));
y(int_local)(int_local) := false; y(int_north)(int_north) := false;
y(int_east)(int_east) := false; y(int_south)(int_south) := false;
y(int_west)(int_west) := false;
end if;
-- Always exclude U-turns for Z-direction
y(int_up)(int_up) := false;
y(int_down)(int_down) := false;
return y;
end function;
end package body TURNS_3D_NOC;

114
noc_files/arbiter.vhd Normal file
View file

@ -0,0 +1,114 @@
-------------------------------------------------------------------------------
-- Title : Centralized arbiter
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : arbiter.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-11-28
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Centralized arbiter, made up of an virtual channel and an switch
-- allocator. Poss routes are exploited to heavily reduce compl.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-28 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.NOC_3D_PACKAGE.all;
entity arbiter is
generic (
port_num : positive := 7;
-- Integer range has to be / is (0 to port_num-1)
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
rout_algo : string := "XYZ_ref";
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) )
);
port (
clk, rst : in std_logic;
header : in header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
crossbar_ctrl : out std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
vc_transfer_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
vc_write_tx_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0));
end entity arbiter;
architecture structural of arbiter is
signal vc_transfer_vec_int : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal input_vc_in_use : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal crossbar_ctrl_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)*
bit_width(port_num-1)-1 downto 0);
signal output_vc_in_use : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
signal vc_sel_enc_vec : vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
begin -- architecture structural
--vc_allocator_1 : entity work.vc_allocator -- use the less cmplx/performant one
vc_allocator_1 : entity work.vc_allocator_high_perf -- use the more cmplx/performant one
generic map (
port_num => port_num,
port_exist => port_exist,
Xis => Xis,
Yis => Yis,
Zis => Zis,
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec)
port map (
clk => clk,
rst => rst,
header => header,
enr_vc => vc_transfer_vec_int,
valid_data_vc_vec => valid_data_vc_vec,
input_vc_in_use => input_vc_in_use,
crossbar_ctrl_vec => crossbar_ctrl_vec,
vc_sel_enc_vec => vc_sel_enc_vec,
output_vc_in_use => output_vc_in_use);
switch_allocator_1 : entity work.switch_allocator
generic map (
port_num => port_num,
port_exist => port_exist,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec,
vc_depth_array => vc_depth_array,
vc_depth_out_array => vc_depth_out_array,
rout_algo => rout_algo)
port map (
clk => clk,
rst => rst,
input_vc_in_use => input_vc_in_use,
output_vc_in_use => output_vc_in_use,
crossbar_ctrl_vec => crossbar_ctrl_vec,
vc_sel_enc_vec => vc_sel_enc_vec,
valid_data_vc_vec => valid_data_vc_vec,
incr_rx_vec => incr_rx_vec,
crossbar_ctrl => crossbar_ctrl,
vc_transfer_vec => vc_transfer_vec_int,
vc_write_tx_vec => vc_write_tx_vec);
vc_transfer_vec <= vc_transfer_vec_int;
end architecture structural;

64
noc_files/credit_count_single.vhd Normal file
View file

@ -0,0 +1,64 @@
-------------------------------------------------------------------------------
-- Title : Credit counter for one vc in an output port (physcial channel)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : credit_count_single.vhd
-- Author : Lennart Bamberg <lennart@t440s>
-- Company :
-- Created : 2018-11-19
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Uses increment and vc_write_tx to determine if another flit can
-- be written to the VC in the input prot of teh adjacent router.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-19 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity credit_count_single is
generic (
-- buffer space in output vc at the other router
vc_depth_out : positive := 4
);
port(
clk, rst : in std_logic;
incr_rx : in std_logic;
vc_write_tx : in std_logic;
credit_avail : out std_logic);
end entity credit_count_single;
architecture rtl of credit_count_single is
signal count_val : unsigned(bit_width(vc_depth_out+1)-1 downto 0);
signal credit_avail_int : std_logic;
begin -- architecture rtl
process(clk, rst)
begin
if rst = RST_LVL then
count_val <= to_unsigned(vc_depth_out, count_val'length);
elsif rising_edge(clk) then
if incr_rx = '1' and vc_write_tx = '0' then
count_val <= count_val +1;
elsif incr_rx = '0' and vc_write_tx = '1' then
count_val <= count_val - 1;
end if;
end if;
end process;
credit_avail_int <= '1' when count_val > 0 else '0';
-- potential infinite loop if output is not pipelined!
credit_avail <= credit_avail_int or incr_rx;
-- to avoid infinite loop ...
-- credit_avail <= credit_avail_int;
end architecture rtl;

84
noc_files/crossbar.vhd Normal file
View file

@ -0,0 +1,84 @@
-------------------------------------------------------------------------------
-- Title : Mux-based crossbar
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : crossbar.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Crossbar to connect the inputs to the outputs with the help of
-- multiplexers (U-turns are avoided). Poss routes are exploited.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
use work.TURNS_3D_NOC.all;
entity crossbar is
generic(port_num : positive := 7;
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
rout_algo : string := "DXYU");
port (crossbar_in : in flit_vector(port_num-1 downto 0);
crossbar_ctrl : in std_logic_vector(
port_num*bit_width(port_num-1)-1 downto 0);
crossbar_out : out flit_vector(port_num-1 downto 0));
end entity crossbar;
architecture rtl of crossbar is
constant poss_routes : turn_table_3D := routes_3D(rout_algo);
constant port_sel_width : positive := bit_width(port_num-1); -- bits for
-- crossbar_ctrl signal of
-- one output port
type multiplexer_input_type is array (port_num-1 downto 0)
of flit_vector(port_num-2 downto 0);
signal multiplexer_input : multiplexer_input_type;
begin
-------------------------------------------------------------------------------
-- Generate only the inputs that are really required. For all others, choose a
-- don't care (in hardware: just wires)----------------------------------------
-------------------------------------------------------------------------------
INPUT_GEN : process(crossbar_in)
variable var_in : natural;
begin
multiplexer_input <= (others => (others => (others => '-')));
for y in 0 to port_num-1 loop -- For the mulitplexer at output y,
for x in 0 to port_num-2 loop -- the x^th input is
if y+x < port_num-1 then
var_in := y+x+1;
else
var_in := y+x-port_num+1;
end if;
if poss_routes(port_exist(var_in))(port_exist(y)) then
multiplexer_input(y)(x) <= crossbar_in(var_in);
end if;
end loop;
end loop;
end process;
-------------------------------------------------------------------------------
-- Generate the muxes----------------------------------------------------------
-------------------------------------------------------------------------------
MULT_GEN : for i in 0 to port_num-1 generate
begin
crossbar_out(i) <= multiplexer_input(i)(
to_integer(unsigned(
crossbar_ctrl((i+1)*port_sel_width-1 downto i*port_sel_width))));
end generate;
end architecture rtl;

61
noc_files/crossbar_full.vhd Normal file
View file

@ -0,0 +1,61 @@
-------------------------------------------------------------------------------
-- Title : Mux-based crossbar (full connectivity)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : crossbar_full.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Crossbar to connect the inputs to the outputs with the help of
-- multiplexers (U-turns are avoided).
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity crossbar_full is
generic(port_num : positive := 7);
port (crossbar_in : in flit_vector(port_num-1 downto 0);
crossbar_ctrl : in std_logic_vector(
port_num*bit_width(port_num-1)-1 downto 0);
crossbar_out : out flit_vector(port_num-1 downto 0));
end entity crossbar_full;
architecture rtl of crossbar_full is
constant port_sel_width : positive := bit_width(port_num-1); -- bits for the
-- crossbar_ctrl signal of
-- one output port
type multiplexer_input_type is array (port_num-1 downto 0)
of flit_vector(port_num-2 downto 0);
signal multiplexer_input : multiplexer_input_type;
begin
multiplexer_input(0) <= crossbar_in(port_num-1 downto 1);
INPUT_GEN : for i in 1 to port_num-1 generate
begin
multiplexer_input(i) <= crossbar_in(i-1 downto 0)
& crossbar_in(port_num-1 downto i+1);
end generate;
MULT_GEN : for i in 0 to port_num-1 generate
begin
crossbar_out(i) <= multiplexer_input(i)(to_integer(
unsigned(crossbar_ctrl((i+1)*port_sel_width-1 downto i*port_sel_width)))
);
end generate;
end architecture rtl;

67
noc_files/dxyu_routing.vhd Normal file
View file

@ -0,0 +1,67 @@
-------------------------------------------------------------------------------
-- Title : Down-X-Y-Up routing for a router at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : dxyu_routing.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity dxyu_routing is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end dxyu_routing;
architecture rtl of dxyu_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.z_dest)) < Zis) then
routing(int_down) <= '1'; -- Route Down
elsif (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
elsif (to_integer(unsigned(address.z_dest)) > Zis) then
routing(int_up) <= '1'; -- Route pos. Z
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;

81
noc_files/fifo.vhd Normal file
View file

@ -0,0 +1,81 @@
-------------------------------------------------------------------------------
-- Title : FiFo buffer regular (no moving of data in buffer;
-- for credit based flow-control)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : fifo.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-05-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Buffer to read or write one flit (credit-based flow ctrl)
-- when read_enable is set the first word is already fetched in
-- the same clock cycle (NOT THE NEXT CYCLE!)
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-05-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.NOC_3D_PACKAGE.all;
entity fifo is
generic (
buff_depth : integer := 4); -- buffer depths
port (
data_in : in flit; -- Data in
write_en : in std_logic; -- Write enable
read_en : in std_logic; -- Read enable
clk, rst : in std_logic;
data_out : out flit; -- Output data
valid_data : out std_logic); -- Buffer not empty
end entity fifo;
architecture rtl of fifo is
signal read_pointer, write_pointer :
unsigned(bit_width(buff_depth)-1 downto 0);
type buffer_type is array (buff_depth-1 downto 0) of flit;
signal fifo : buffer_type;
begin
-- BUFFER + READ/WRITE POINTER
process(clk, rst)
begin
if rst = RST_LVL then
write_pointer <= (others => '0');
read_pointer <= (others => '0');
fifo <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if write_en = '1' then
fifo(to_integer(write_pointer)) <= data_in;
write_pointer <= (write_pointer + 1) mod buff_depth;
end if;
if read_en = '1' then
read_pointer <= (read_pointer + 1) mod buff_depth;
end if;
end if;
end process;
data_out <= fifo(to_integer(read_pointer));
process(clk, rst)
begin
if rst = RST_LVL then
valid_data <= '0';
elsif clk = '1' and clk'event then
if write_en = '1' then
valid_data <= '1';
elsif (write_pointer = ((read_pointer+1) mod buff_depth) and read_en = '1')
or (buff_depth = 1 and read_en = '1') then
valid_data <= '0';
end if;
end if;
end process;
end architecture;

5012
noc_files/full_noc.vhd Normal file
View file

File diff suppressed because it is too large Load diff

165
noc_files/header_arbiter_and_decoder.vhd Normal file
View file

@ -0,0 +1,165 @@
-------------------------------------------------------------------------------
-- Title : Header arbiter and decoder
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : header_arbiter_and_decoder.vhd
-- Author : Lennart Bamberg <lennart@x230>
-- Company :
-- Created : 2018-11-05
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Arbitrate next VC in the input to be assigned to an output VC.
-- For the granted input the routing is calculated, and the request
-- to the output is made. Also a counter with the packet length is
-- set. Via enable-read (enr_vc) the end of the packet is trackes,
-- which indicated that the next valid flit in the input vc will be
-- teh head-flit of a new package (new arbitration).
-- COMMENTS:
-- We have a 'strong' fifo fairness. Thus, if one packet
-- is blocked and it waits in the only virtual channel that wasn't
-- recently served, we wait for the blocking to be solved!
-- For a week fairness (with potentially a higher throughput) set
-- "ack" of the RR-arbiter to constant '1'.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-05 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
use work.TURNS_3D_NOC.all;
entity header_arbiter_and_decoder is
generic (Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
port_num : integer := 7;
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
port_is : integer := 1; -- current port
vc_num : positive := 4;
header_incl_in_packet_length : boolean := true;
rout_algo : string := "DXYU");
port (
clk, rst : in std_logic;
header : in header_inf_vector(vc_num-1 downto 0);
valid_data_vc : in std_logic_vector(vc_num-1 downto 0);
enr_vc : in std_logic_vector(vc_num-1 downto 0); -- ONE-HOT
ack_vc : in std_logic; -- acknowledge of vc allocation
granted_rq : out std_logic_vector(port_num-1 downto 0);
input_vc_in_use : out std_logic_vector(vc_num-1 downto 0);
-- indicate if a vc is free again in the next cc
packet_end : out std_logic_vector(vc_num-1 downto 0);
granted_vc : out std_logic_vector(vc_num-1 downto 0)
);
end header_arbiter_and_decoder;
architecture rtl of header_arbiter_and_decoder is
constant poss_routes : turn_table_3D := routes_3D(rout_algo);
signal new_package_vc, grant : std_logic_vector(vc_num-1 downto 0);
signal flit_count_0, flit_count_1 : std_logic_vector(vc_num-1 downto 0);
type flit_counter_vector is array(vc_num-1 downto 0) of
unsigned(packet_len_width-1 downto 0);
signal flit_count_values : flit_counter_vector;
signal header_nxt : header_inf; -- current analyzed header
signal address_nxt : address_inf; -- current analyzed header
signal routing_en : std_logic;
signal granted_rq_cmplt : std_logic_vector(6 downto 0);
signal allocated : std_logic_vector(vc_num-1 downto 0);
signal packet_length_nxt : std_logic_vector(packet_len_width-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Check if in any VC a new package has to be en encoded and also if in the
-- next clock cycle any VV becomes free again--------------------------------
-----------------------------------------------------------------------------
GEN_COUNT_EQ_ZERO : for i in 0 to vc_num-1 generate
flit_count_0(i) <= '1' when (flit_count_values(i) = to_unsigned(0, packet_len_width))
else '0';
flit_count_1(i) <= '1' when (flit_count_values(i) = to_unsigned(1, packet_len_width))
else '0'; -- Only req 1 extra gate to flit_count_0
end generate;
input_vc_in_use <= not(flit_count_0);
packet_end <= flit_count_1 and enr_vc;
new_package_vc <= flit_count_0 and valid_data_vc;
-----------------------------------------------------------------------------
-- Round robin arbitration between all new packages -------------------------
-----------------------------------------------------------------------------
GEN_RR : if vc_num > 1 generate
-- to add an extra pipeline stage for the rout_algo just intanciate
-- "rr_arbiter" instead of "rr_arbiter_no_delay" ??
rr_arbiter_no_delay_1 : entity work.rr_arbiter_no_delay
generic map (
CNT => vc_num)
port map (
clk => clk,
rst => rst,
req => new_package_vc,
ack => ack_vc,
grant => grant);
header_nxt <= header(one_hot2int(grant)); -- next header to be decoded
end generate;
GEN_PASS_NO_VC : if vc_num = 1 generate
grant <= new_package_vc;
header_nxt <= header(0);
end generate;
address_nxt <= extract_address_inf(header_nxt);
packet_length_nxt <= header_nxt.packet_length;
routing_en <= or_reduce(grant);
granted_vc <= grant;
-----------------------------------------------------------------------------
---------------------------- Routing computation ----------------------------
-----------------------------------------------------------------------------
routing_calc_1 : entity work.routing_calc
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis,
rout_algo => rout_algo)
port map (
address => address_nxt,
enable => routing_en,
routing => granted_rq_cmplt);
--check which routes are actually possible. Set non-possible 0
process(granted_rq_cmplt)
begin
granted_rq <= (others => '0');
for i in 0 to port_num-1 loop
if poss_routes(port_is)(port_exist(i)) then
granted_rq(i) <= granted_rq_cmplt(port_exist(i));
end if;
end loop;
end process;
allocated <= (others => '0') when ack_vc = '0' else grant;
-----------------------------------------------------------------------------
-- Generate the storage Elements, including the flit counter ----------------
-----------------------------------------------------------------------------
STOR_GEN : for i in 0 to vc_num-1 generate
seq_packet_counter_i : entity work.seq_packet_counter
generic map (
header_incl_in_packet_length => header_incl_in_packet_length)
port map (
clk => clk,
rst => rst,
allocated => allocated(i),
packet_len => header_nxt.packet_length,
enr_vc => enr_vc(i),
flit_count => flit_count_values(i));
end generate;
end rtl;

66
noc_files/output_register.vhd Normal file
View file

@ -0,0 +1,66 @@
-------------------------------------------------------------------------------
-- Title : Output register for the the link
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : output_register.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-25
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Just a pipeline stage for the link.
-- "pl" indicates a pipelined signal.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-25 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
entity output_register is
generic(
vc_num : positive := 4; -- Number of VCs in the according
-- input buffer
vc_num_out : positive := 4); -- Number of VC in the input buffer at
-- the other side of the link
port(
clk, rst : in std_logic;
data_tx : in std_logic_vector(flit_size-1 downto 0);
vc_write_tx : in std_logic_vector(
vc_num_out-1 downto 0);
incr_tx : in std_logic_vector(vc_num-1 downto 0);
data_tx_pl : out std_logic_vector(flit_size-1 downto 0);
vc_write_tx_pl : out std_logic_vector(vc_num_out-1 downto 0);
incr_tx_pl : out std_logic_vector(vc_num-1 downto 0)
);
end output_register;
architecture rtl of output_register is
begin
-- Flip-Flops enabled by req-transfer to reduce the switching activity
process(clk, rst)
begin
if rst = RST_LVL then
data_tx_pl <= (others => '0');
vc_write_tx_pl <= (others => '0');
incr_tx_pl <= (others => '0');
elsif rising_edge(clk) then
if or_reduce(vc_write_tx) = '1' then
data_tx_pl <= data_tx;
end if;
incr_tx_pl <= incr_tx;
vc_write_tx_pl <= vc_write_tx;
end if;
end process;
end rtl;

94
noc_files/packet_injector_package.vhd Normal file
View file

@ -0,0 +1,94 @@
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : packet_injector_package.vhd
-- Author : Behnam Razi Perjikolaei <raziperj@uni-bremen.de>
-- Company :
-- Created : 2019-06-20
-- Last update: 2019-06-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-06-20 1.0 behnam Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
------------------------------------------------------------------------------------------
package packet_injector_package is
constant max_packet_num : positive := 31;
function rand_destination (seed_1 : positive; seed_2 : positive; layer_prob : integer_vec)
return address_inf;
function find_int (int_vec : integer_vec; int_val : integer)
return boolean;
end packet_injector_package;
------------------------------------------------------------------------------------------
package body packet_injector_package is
-- purpose: generate random node address by considering probability of each layer
function rand_destination (
seed_1 : positive;
seed_2 : positive;
layer_prob : integer_vec)
return address_inf is
variable x_rand, y_rand, z_rand : real;
variable x_range : real := real(max_x_dim);
variable y_range : real := real(max_y_dim);
variable z_range : real := 100.0;
variable z_prob_min, z_prob_max : integer range 0 to 100;
variable x_rand_num, y_rand_num, z_rand_num : integer range 0 to 100;
variable dest_addr : address_inf;
variable seed1, seed2 : positive;
begin -- rand_destination
seed1 := seed_1;
seed2 := seed_2;
uniform(seed1, seed2, z_rand);
z_rand_num := integer(z_rand*z_range);
uniform(seed1, seed2, y_rand);
y_rand_num := integer(y_rand*y_range);
uniform(seed1, seed2, x_rand);
x_rand_num := integer(x_rand*x_range);
z_prob_max := 0;
for i in layer_prob'range loop
z_prob_min := z_prob_max;
z_prob_max := z_prob_min+layer_prob(i);
if z_rand_num <= z_prob_max and z_rand_num >= z_prob_min then
dest_addr.z_dest := std_logic_vector(to_unsigned(i, positive(ceil(log2(real(max_z_dim))))));
dest_addr.y_dest := std_logic_vector(to_unsigned(y_rand_num, positive(ceil(log2(real(max_y_dim))))));
dest_addr.x_dest := std_logic_vector(to_unsigned(x_rand_num, positive(ceil(log2(real(max_x_dim))))));
end if;
end loop; -- i
return dest_addr;
end rand_destination;
-- purpose: find an integer value in an integer vector and return true or false
function find_int (
int_vec : integer_vec;
int_val : integer)
return boolean is
variable find_result : boolean := false;
begin -- find_int
for i in 0 to int_vec'length-1 loop
if int_vec(i) = int_val then
find_result := true;
end if;
end loop; -- i
return find_result;
end find_int;
end packet_injector_package;
------------------------------------------------------------------------------------------

121
noc_files/router.vhd Normal file
View file

@ -0,0 +1,121 @@
-------------------------------------------------------------------------------
-- Title : Router with non buffered outputs (no pipeline)
-- Project :
-------------------------------------------------------------------------------
-- File : router.vhd
-- Author : Lennart Bamberg <lennart@t440s>
-- Company :
-- Created : 2018-11-23
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-23 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.NOC_3D_PACKAGE.all;
entity router is
generic (
port_num : integer := 7;
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
-- integer vector of range "0 to port_num-1"
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
rout_algo : string := "DXYU"
);
port (
-- Inputs
clk, rst : in std_logic;
data_rx : in flit_vector(port_num-1 downto 0);
vc_write_rx_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Outputs
data_tx : out flit_vector(port_num-1 downto 0);
vc_write_tx_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
incr_tx_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0));
end entity router;
architecture structural of router is
signal vc_transfer_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal valid_data_vc_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_transfer : flit_vector(port_num-1 downto 0);
signal header : header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal crossbar_ctrl : std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
begin -- architecture structural
INBUT_BUFFS : for i in 0 to port_num-1 generate
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
vc_input_buffer_i : entity work.vc_input_buffer
generic map (
vc_num => vc_num_vec(i),
vc_depth => vc_depth_array(i))
port map (
clk => clk,
rst => rst,
data_rx => data_rx(i),
vc_write_rx => vc_write_rx_vec(ur_vc downto lr_vc),
vc_transfer => vc_transfer_vec(ur_vc downto lr_vc),
valid_data_vc => valid_data_vc_vec(ur_vc downto lr_vc),
data_transfer => data_transfer(i),
header => header(ur_vc downto lr_vc));
end generate;
XBAR : entity work.crossbar
generic map (
port_num => port_num,
port_exist => port_exist,
rout_algo => rout_algo)
port map (
crossbar_in => data_transfer,
crossbar_ctrl => crossbar_ctrl,
crossbar_out => data_tx);
CTRL_ARB : entity work.arbiter
generic map (
port_num => port_num,
port_exist => port_exist,
Xis => Xis,
Yis => Yis,
Zis => Zis,
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec,
vc_depth_array => vc_depth_array,
vc_depth_out_array => vc_depth_out_array)
port map (
clk => clk,
rst => rst,
header => header,
valid_data_vc_vec => valid_data_vc_vec,
incr_rx_vec => incr_rx_vec,
crossbar_ctrl => crossbar_ctrl,
vc_transfer_vec => vc_transfer_vec,
vc_write_tx_vec => vc_write_tx_vec);
end architecture structural;

150
noc_files/router_fast.vhd Normal file
View file

@ -0,0 +1,150 @@
-------------------------------------------------------------------------------
-- Title : Router with buffered outputs (pipeline stage)
-- Project :
-------------------------------------------------------------------------------
-- File : router_full.vhd
-- Author : Behnam Razi
-- Company :
-- Created : 2019-03-12
-- Last update: 2019-03-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-12 1.0 Behnam Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_MISC.all;
use work.NOC_3D_PACKAGE.all;
entity router_fast is
generic (
port_num : integer := 7;
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
-- integer vector of range "0 to port_num-1"
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
rout_algo : string := "DXYU"
);
port (
-- Inputs
clk, rst : in std_logic;
data_rx : in std_logic_vector(port_num*flit_size-1 downto 0);
vc_write_rx_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Outputs
data_tx_pl : out std_logic_vector(port_num*flit_size-1 downto 0);
vc_write_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
incr_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0));
end entity router_fast;
architecture structural of router_fast is
signal vc_transfer_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_rx_sep : flit_vector(port_num-1 downto 0);
signal data_tx_sep : flit_vector(port_num-1 downto 0);
signal valid_data_vc_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_transfer, data_tx : flit_vector(port_num-1 downto 0);
signal header : header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal crossbar_ctrl : std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
signal vc_write_tx_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
begin -- architecture structural
SEP_GEN: for i in 0 to port_num-1 generate
begin
data_rx_sep(i) <= data_rx((i+1)*flit_size-1 downto i*flit_size);
data_tx_pl((i+1)*flit_size-1 downto i*flit_size) <= data_tx_sep(i);
end generate;
INBUT_BUFFS : for i in 0 to port_num-1 generate
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
vc_input_buffer_i : entity work.vc_input_buffer
generic map (
vc_num => vc_num_vec(i),
vc_depth => vc_depth_array(i))
port map (
clk => clk,
rst => rst,
data_rx => data_rx_sep(i),
vc_write_rx => vc_write_rx_vec(ur_vc downto lr_vc),
vc_transfer => vc_transfer_vec(ur_vc downto lr_vc),
valid_data_vc => valid_data_vc_vec(ur_vc downto lr_vc),
data_transfer => data_transfer(i),
header => header(ur_vc downto lr_vc));
end generate;
XBAR : entity work.crossbar
generic map ( port_num => port_num,
port_exist => port_exist,
rout_algo => rout_algo)
port map (
crossbar_in => data_transfer,
crossbar_ctrl => crossbar_ctrl,
crossbar_out => data_tx);
OUT_PL_REG : for i in 0 to port_num-1 generate
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
output_register_i : entity work.output_register
generic map (
vc_num => vc_num_vec(i),
vc_num_out => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
data_tx => data_tx(i),
vc_write_tx => vc_write_tx_vec(ur_vc_out downto lr_vc_out),
incr_tx => vc_transfer_vec(ur_vc downto lr_vc),
data_tx_pl => data_tx_sep(i),
vc_write_tx_pl => vc_write_tx_pl_vec(ur_vc_out downto lr_vc_out),
incr_tx_pl => incr_tx_pl_vec(ur_vc downto lr_vc));
end generate;
CTRL_ARB : entity work.arbiter
generic map (
port_num => port_num,
port_exist => port_exist,
Xis => Xis,
Yis => Yis,
Zis => Zis,
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec,
vc_depth_array => vc_depth_array,
vc_depth_out_array => vc_depth_out_array)
port map (
clk => clk,
rst => rst,
header => header,
valid_data_vc_vec => valid_data_vc_vec,
incr_rx_vec => incr_rx_vec,
crossbar_ctrl => crossbar_ctrl,
vc_transfer_vec => vc_transfer_vec,
vc_write_tx_vec => vc_write_tx_vec);
end architecture structural;

150
noc_files/router_fast_110.vhd Normal file
View file

@ -0,0 +1,150 @@
-------------------------------------------------------------------------------
-- Title : Router with buffered outputs (pipeline stage)
-- Project :
-------------------------------------------------------------------------------
-- File : router_full.vhd
-- Author : Behnam Razi
-- Company :
-- Created : 2019-03-12
-- Last update: 2019-09-09
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-12 1.0 Behnam Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_MISC.all;
use work.NOC_3D_PACKAGE.all;
entity router_fast_110 is
generic (
port_num : integer := 6;
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 0;
header_incl_in_packet_length : boolean := true;
-- integer vector of range "0 to port_num-1"
port_exist : integer_vec := (0, 1, 2, 3, 4, 5);
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4);
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4);
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ));
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ));
rout_algo : string := "DXYU"
);
port (
-- Inputs
clk, rst : in std_logic;
data_rx : in std_logic_vector(port_num*flit_size-1 downto 0);
vc_write_rx_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Outputs
data_tx_pl : out std_logic_vector(port_num*flit_size-1 downto 0);
vc_write_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
incr_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0));
end entity router_fast_110;
architecture structural of router_fast_110 is
signal vc_transfer_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_rx_sep : flit_vector(port_num-1 downto 0);
signal data_tx_sep : flit_vector(port_num-1 downto 0);
signal valid_data_vc_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_transfer, data_tx : flit_vector(port_num-1 downto 0);
signal header : header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal crossbar_ctrl : std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
signal vc_write_tx_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
begin -- architecture structural
SEP_GEN: for i in 0 to port_num-1 generate
begin
data_rx_sep(i) <= data_rx((i+1)*flit_size-1 downto i*flit_size);
data_tx_pl((i+1)*flit_size-1 downto i*flit_size) <= data_tx_sep(i);
end generate;
INBUT_BUFFS : for i in 0 to port_num-1 generate
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
vc_input_buffer_i : entity work.vc_input_buffer
generic map (
vc_num => vc_num_vec(i),
vc_depth => vc_depth_array(i))
port map (
clk => clk,
rst => rst,
data_rx => data_rx_sep(i),
vc_write_rx => vc_write_rx_vec(ur_vc downto lr_vc),
vc_transfer => vc_transfer_vec(ur_vc downto lr_vc),
valid_data_vc => valid_data_vc_vec(ur_vc downto lr_vc),
data_transfer => data_transfer(i),
header => header(ur_vc downto lr_vc));
end generate;
XBAR : entity work.crossbar
generic map ( port_num => port_num,
port_exist => port_exist,
rout_algo => rout_algo)
port map (
crossbar_in => data_transfer,
crossbar_ctrl => crossbar_ctrl,
crossbar_out => data_tx);
OUT_PL_REG : for i in 0 to port_num-1 generate
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
output_register_i : entity work.output_register
generic map (
vc_num => vc_num_vec(i),
vc_num_out => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
data_tx => data_tx(i),
vc_write_tx => vc_write_tx_vec(ur_vc_out downto lr_vc_out),
incr_tx => vc_transfer_vec(ur_vc downto lr_vc),
data_tx_pl => data_tx_sep(i),
vc_write_tx_pl => vc_write_tx_pl_vec(ur_vc_out downto lr_vc_out),
incr_tx_pl => incr_tx_pl_vec(ur_vc downto lr_vc));
end generate;
CTRL_ARB : entity work.arbiter
generic map (
port_num => port_num,
port_exist => port_exist,
Xis => Xis,
Yis => Yis,
Zis => Zis,
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec,
vc_depth_array => vc_depth_array,
vc_depth_out_array => vc_depth_out_array)
port map (
clk => clk,
rst => rst,
header => header,
valid_data_vc_vec => valid_data_vc_vec,
incr_rx_vec => incr_rx_vec,
crossbar_ctrl => crossbar_ctrl,
vc_transfer_vec => vc_transfer_vec,
vc_write_tx_vec => vc_write_tx_vec);
end architecture structural;

142
noc_files/router_pl.vhd Normal file
View file

@ -0,0 +1,142 @@
-------------------------------------------------------------------------------
-- Title : Router with buffered outputs (pipeline stage)
-- Project :
-------------------------------------------------------------------------------
-- File : router_pl.vhd
-- Author : Lennart Bamberg <lennart@t440s>
-- Company :
-- Created : 2018-11-23
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-23 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.NOC_3D_PACKAGE.all;
entity router_pl is
generic (
port_num : integer := 7;
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
-- integer vector of range "0 to port_num-1"
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
rout_algo : string := "DXYU"
);
port (
-- Inputs
clk, rst : in std_logic;
data_rx : in flit_vector(port_num-1 downto 0);
vc_write_rx_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Outputs
data_tx_pl : out flit_vector(port_num-1 downto 0);
vc_write_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
incr_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0));
end entity router_pl;
architecture structural of router_pl is
signal vc_transfer_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal valid_data_vc_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal data_transfer, data_tx : flit_vector(port_num-1 downto 0);
signal header : header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal crossbar_ctrl : std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
signal vc_write_tx_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
begin -- architecture structural
INBUT_BUFFS : for i in 0 to port_num-1 generate
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
vc_input_buffer_i : entity work.vc_input_buffer
generic map (
vc_num => vc_num_vec(i),
vc_depth => vc_depth_array(i))
port map (
clk => clk,
rst => rst,
data_rx => data_rx(i),
vc_write_rx => vc_write_rx_vec(ur_vc downto lr_vc),
vc_transfer => vc_transfer_vec(ur_vc downto lr_vc),
valid_data_vc => valid_data_vc_vec(ur_vc downto lr_vc),
data_transfer => data_transfer(i),
header => header(ur_vc downto lr_vc));
end generate;
XBAR : entity work.crossbar
generic map (
port_num => port_num,
port_exist => port_exist,
rout_algo => rout_algo)
port map (
crossbar_in => data_transfer,
crossbar_ctrl => crossbar_ctrl,
crossbar_out => data_tx);
OUT_PL_REG : for i in 0 to port_num-1 generate
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
output_register_i : entity work.output_register
generic map (
vc_num => vc_num_vec(i),
vc_num_out => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
data_tx => data_tx(i),
vc_write_tx => vc_write_tx_vec(ur_vc_out downto lr_vc_out),
incr_tx => vc_transfer_vec(ur_vc downto lr_vc),
data_tx_pl => data_tx_pl(i),
vc_write_tx_pl => vc_write_tx_pl_vec(ur_vc_out downto lr_vc_out),
incr_tx_pl => incr_tx_pl_vec(ur_vc downto lr_vc));
end generate;
CTRL_ARB : entity work.arbiter
generic map (
port_num => port_num,
port_exist => port_exist,
Xis => Xis,
Yis => Yis,
Zis => Zis,
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo,
vc_num_vec => vc_num_vec,
vc_num_out_vec => vc_num_out_vec,
vc_depth_array => vc_depth_array,
vc_depth_out_array => vc_depth_out_array)
port map (
clk => clk,
rst => rst,
header => header,
valid_data_vc_vec => valid_data_vc_vec,
incr_rx_vec => incr_rx_vec,
crossbar_ctrl => crossbar_ctrl,
vc_transfer_vec => vc_transfer_vec,
vc_write_tx_vec => vc_write_tx_vec);
end architecture structural;

95
noc_files/routing_calc.vhd Normal file
View file

@ -0,0 +1,95 @@
-------------------------------------------------------------------------------
-- Title : Routing calc at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : routing_calc.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-14
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity routing_calc is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
rout_algo : string := "DXYU");
port(
address : in address_inf;
enable : in std_logic;
routing : out std_logic_vector(6 downto 0));
end routing_calc;
architecture rtl of routing_calc is
begin
ROUTING_DXYU : if rout_algo = "DXYU" generate
dxyu_routing_1 : entity work.dxyu_routing
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis)
port map (
address => address,
enable => enable,
routing => routing);
end generate;
ROUTING_UXYD : if rout_algo = "UXYD" generate
dxyu_routing_1 : entity work.uxyd_routing
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis)
port map (
address => address,
enable => enable,
routing => routing);
end generate;
ROUTING_XYZ : if rout_algo = "XYZ" or rout_algo = "XYZ_ref"
or rout_algo = "XYZ_REF" generate
dxyu_routing_1 : entity work.xyz_routing
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis)
port map (
address => address,
enable => enable,
routing => routing);
end generate;
ROUTING_ZXY : if rout_algo = "ZXY" generate
dxyu_routing_1 : entity work.zxy_routing
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis)
port map (
address => address,
enable => enable,
routing => routing);
end generate;
end architecture;

103
noc_files/rr_arbiter.vhd Normal file
View file

@ -0,0 +1,103 @@
-------------------------------------------------------------------------------
-- Title : Round Robin arbiter
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : NOC_3D_PACKAGE.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package including the constants, types, function and components
-- required for the modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- HUGE PARTS OF THIS FILE ARE ADOPTED FROM A FILE BY BENJAMIN KRILL, DISTRI-
-- BUTED USING THE FOLLOWING COPYRIGHT NOTE:
-- Copyright (c) 2009 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-XX-XX 0.0 krll Created
-- 2018-10-24 1.0 bamberg Modified for 3D NoC project
-------------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity rr_arbiter is
generic (CNT : integer := 7);
port (
clk : in std_logic;
rst : in std_logic;
req : in std_logic_vector(CNT-1 downto 0);
ack : in std_logic;
grant : out std_logic_vector(CNT-1 downto 0)
);
end;
architecture rr_arbiter of rr_arbiter is
signal grant_q : std_logic_vector(CNT-1 downto 0);
signal pre_req : std_logic_vector(CNT-1 downto 0);
signal sel_gnt : std_logic_vector(CNT-1 downto 0);
signal isol_lsb : std_logic_vector(CNT-1 downto 0);
signal mask_pre : std_logic_vector(CNT-1 downto 0);
signal win : std_logic_vector(CNT-1 downto 0);
begin
grant <= grant_q;
-- Mask off previous winners
mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req);
-- Select new winner
sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1);
-- Isolate least significant set bit.
isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1);
win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb;
process (clk, rst)
begin
if rst = RST_LVL then
pre_req <= (others => '0');
grant_q <= (others => '0');
elsif rising_edge(clk) then
--grant_q <= grant_q; -- WHY SHOULD IT BE NESSECARY??
--pre_req <= pre_req; -- WHY SHOULD IT BE NESSECARY??
if grant_q = (CNT-1 downto 0 => '0') or ack = '1' then
--if win /= (CNT-1 downto 0 => '0') then -- maybe comment it to reduce
-- complexity, then, if no
-- request is left, the mask
-- would be just reset. This
-- will even increse flit/packet level
-- fairness (decr. port fairness)
pre_req <= win;
--end if;
grant_q <= win;
end if;
end if;
end process;
end rr_arbiter;

90
noc_files/rr_arbiter_no_delay.vhd Normal file
View file

@ -0,0 +1,90 @@
-------------------------------------------------------------------------------
-- Title : Round Robin arbiter
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : NOC_3D_PACKAGE.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- HUGE PARTS OF THIS FILE ARE ADOPTED FROM A FILE BY BENJAMIN KRILL, DISTRI-
-- BUTED USING THE FOLLOWING COPYRIGHT NOTE:
-- Copyright (c) 2009 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-XX-XX 0.0 krll Created
-- 2018-10-24 1.0 bamberg Modified for 3D NoC project
-------------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity rr_arbiter_no_delay is
generic (CNT : integer := 7);
port (
clk : in std_logic;
rst : in std_logic;
req : in std_logic_vector(CNT-1 downto 0);
ack : in std_logic;
grant : out std_logic_vector(CNT-1 downto 0)
);
end;
architecture rr_arbiter_no_delay of rr_arbiter_no_delay is
signal pre_req : std_logic_vector(CNT-1 downto 0);
signal sel_gnt : std_logic_vector(CNT-1 downto 0);
signal isol_lsb : std_logic_vector(CNT-1 downto 0);
signal mask_pre : std_logic_vector(CNT-1 downto 0);
signal win : std_logic_vector(CNT-1 downto 0);
begin
grant <= win;
-- Mask off previous winners
mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req);
-- Select new winner (isolate LSB of the masked req)
sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1);
-- Isolate least significant set bit.
isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1);
win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb;
process (clk, rst)
begin
if rst = RST_LVL then
pre_req <= (others => '0');
elsif rising_edge(clk) then
if ack = '1' then
pre_req <= win;
end if;
end if;
end process;
end rr_arbiter_no_delay;

80
noc_files/seq_packet_counter.vhd Normal file
View file

@ -0,0 +1,80 @@
-------------------------------------------------------------------------------
-- Title : Sequential packet counter
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : seq_packet_counter.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : University of Bremen
-- Created : 2018-11-28
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: When a new packet is assigend, the coutner is set to the packet
-- length. Whenever a flit is transfered, the counter is decr.
-------------------------------------------------------------------------------
-- Copyright (c) 2018 University of Bremen
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-28 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
entity seq_packet_counter is
generic (
header_incl_in_packet_length : boolean := true);
port(
clk, rst : in std_logic;
allocated : in std_logic;
packet_len : in std_logic_vector(packet_len_width-1 downto 0);
enr_vc : in std_logic;
flit_count : out unsigned(packet_len_width-1 downto 0));
end entity seq_packet_counter;
architecture rtl of seq_packet_counter is
signal flit_count_nxt, flit_count_load, flit_count_int
: unsigned(packet_len_width-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Flip Flop Counter --------------------------------------------------------
-----------------------------------------------------------------------------
process(clk, rst)
begin
if rst = RST_LVL then
flit_count_int <= (others => '0');
elsif clk'event and clk = '1' then
if (allocated or enr_vc) = '1' then -- flip flop enable
flit_count_int <= flit_count_nxt;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Combinatorial ------------------------------------------------------------
-----------------------------------------------------------------------------
flit_count_load <= unsigned(packet_len) when header_incl_in_packet_length
else (unsigned(packet_len)+1);
process(allocated, enr_vc, flit_count_int, flit_count_load)
begin
if allocated = '1' and enr_vc = '0' then
flit_count_nxt <= flit_count_load;
elsif allocated = '0' and enr_vc = '1' then
flit_count_nxt <= flit_count_int-1;
else
flit_count_nxt <= (others => '-');
end if;
end process;
flit_count <= flit_count_int;
end architecture;

140
noc_files/srl_fifo.vhd Normal file
View file

@ -0,0 +1,140 @@
-------------------------------------------------------------------------------
-- Title : SRL fifo
-- Project : NoC testbench generator
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-------------------------------------------------------------------------------
-- Copyright (c)
-- Andrew Mulcock, amulcock@opencores.org
-- Copyright (C) 2008 Authors and OPENCORES.ORG
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
-------------------------------------------------------------------------------
-- Additional copyright (c):
-- This file has been edited by Seyed Nima Omidsajedi
-- for the purpose of Traffic_Gen project
-------------------------------------------------------------------------------
-- Vesion : 1.1.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity srl_fifo is
generic ( buffer_depth : integer := 8 );
port(
data_in : in flit;
data_out : out flit;
rst : in std_logic;
write_en : in std_logic;
read_en : in std_logic;
buffer_full : out std_logic;
buffer_empty : out std_logic;
clk : in std_logic
);
end entity ;
architecture rtl of srl_fifo is
constant pointer_vec : positive := bit_width(buffer_depth); -- set to number of bits needed to store pointer = log2(buffer_depth)
type srl_array is array (buffer_depth-1 downto 0) of flit;
signal fifo_store : srl_array;
signal pointer : integer range 0 to buffer_depth - 1;
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal valid_write : std_logic;
signal half_full_int : std_logic_vector( pointer_vec - 1 downto 0);
signal empty : std_logic := '1';
signal valid_count : std_logic ;
begin
-- Valid write_en, high when valid to write_en data to the store.
valid_write <= '1' when ( read_en = '1' and write_en = '1' )
or ( write_en = '1' and pointer_full = '0' ) else '0';
-- data store SRL's
data_srl :process( clk )
begin
if rising_edge( clk ) then
if valid_write = '1' then
fifo_store <= fifo_store( fifo_store'left - 1 downto 0) & data_in;
end if;
end if;
end process;
data_out <= fifo_store( pointer );
process(clk)
begin
if rising_edge( clk ) then
if rst = RST_LVL then
empty <= '1';
elsif empty = '1' and write_en = '1' then
empty <= '0';
elsif pointer_zero = '1' and read_en = '1' and write_en = '0' then
empty <= '1';
end if;
end if;
end process;
-- W R Action
-- 0 0 pointer <= pointer
-- 0 1 pointer <= pointer - 1 read_en, but no write_en, so less data in counter
-- 1 0 pointer <= pointer + 1 write_en, but no read_en, so more data in fifo
-- 1 1 pointer <= pointer read_en and write_en, so same number of words in fifo
valid_count <= '1' when (
(write_en = '1' and read_en = '0' and pointer_full = '0' and empty = '0' )
or
(write_en = '0' and read_en = '1' and pointer_zero = '0' )
) else '0';
process( clk )
begin
if rising_edge( clk ) then
if valid_count = '1' then
if write_en = '1' then
pointer <= pointer + 1;
else
pointer <= pointer - 1;
end if;
end if;
end if;
end process;
-- Detect when pointer is zero and maximum
pointer_zero <= '1' when pointer = 0 else '0';
pointer_full <= '1' when pointer = buffer_depth - 1 else '0';
process(pointer_full)
begin
if (pointer_full = '1') then
report "Internal Buffer is Full!" severity failure;
end if;
end process;
-- assign internal signals to outputs
buffer_full <= pointer_full;
buffer_empty <= empty;
end rtl;
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------

261
noc_files/switch_allocator.vhd Normal file
View file

@ -0,0 +1,261 @@
-------------------------------------------------------------------------------
-- Title : Switch allocator
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : switch_allocator.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-11-15
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Switch allocator witch sets the input to output connections
-- between assigned input VCs (with valid data) and the according
-- outputs VCs (when credit is available).
-------------------------------------------------------------------------------
--Desginer comments: With an encoded vc_transfer and a valid signal the
-- input VC select signal could be determined in advance.
-- Since this is part of the crit. path, it has a potential
-- to enhance timing if we slightly mod. the design (-power).
-- Second possiblity to improve speed would be to pre-calcu-
-- late the next switch allocation. This is realized by
-- simply swapping the regular RR-arbiters by delayed RR-
-- arbiters (see DESIGNER-HINT l. 181). The drawback would be
-- a one clock-cycle bigger initial latency for the first flit
-- of a new package.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-15 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
use work.TURNS_3D_NOC.all;
entity switch_allocator is
generic (
port_num : integer := 7;
-- integer vector of range "0 to port_num-1"
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
rout_algo : string := "DXYU"
);
port(
clk, rst : in std_logic;
-- Inputs from VC allocator
input_vc_in_use : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
output_vc_in_use : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
crossbar_ctrl_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)*
bit_width(port_num-1)-1 downto 0);
vc_sel_enc_vec : in vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Inputs from Input buffer
valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0); --
-- Inputs from Link
incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
-- Output to crossbar
crossbar_ctrl : out std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
-- output to Inbut Buffer (vc_transfer) and output-buffer (incr_tx)
vc_transfer_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
vc_write_tx_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0)
);
end entity switch_allocator;
architecture rtl of switch_allocator is
constant poss_routes : turn_table_3D := routes_3D(rout_algo);
constant sel_width : positive := bit_width(port_num-1);
signal switch_rq : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
signal switch_rq_grant : vc_status_array(port_num-1 downto 0);
signal vc_transfer_vec_int : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
type switch_ack_array is array(port_num-1 downto 0) of std_logic_vector(port_num-1 downto 0);
signal switch_acks : switch_ack_array;
signal switch_ack : std_logic_vector(port_num-1 downto 0);
type crossbar_ctrl_array_type is array(int_vec_sum(vc_num_out_vec)-1 downto 0) of std_logic_vector(sel_width-1 downto 0);
signal crossbar_ctrl_vc_out : crossbar_ctrl_array_type;
type rq_array is array (port_num-1 downto 0) of vc_status_array(port_num-2 downto 0);
signal poss_channel_rq : rq_array;
signal channel_rq, channel_grant : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
signal credit_avail : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
begin -- architecture rtl
-------------------------------------------------------------------------------
-- Transform the crossbar ctrls into an array for better readability ----------
-------------------------------------------------------------------------------
XBAR_CTRL : for i in 0 to int_vec_sum(vc_num_out_vec)-1 generate
crossbar_ctrl_vc_out(i) <= crossbar_ctrl_vec((i+1)*sel_width-1 downto i*sel_width);
end generate;
-------------------------------------------------------------------------------
-- When an input VC is assigned and contains data: a switch request is made ---
-------------------------------------------------------------------------------
switch_rq <= input_vc_in_use and valid_data_vc_vec;
-------------------------------------------------------------------------------
-- For each input VC arbitrate grant one switch request in a RR manner --------
-------------------------------------------------------------------------------
INPUT_ARB_GEN : for i in 0 to port_num-1 generate
constant ur_vc : natural := upper_range(vc_num_vec, i);
constant lr_vc : natural := lower_range(vc_num_vec, i);
begin
PASS_NO_VC : if vc_num_vec(i) = 1 generate -- single vc --> no arb. required
switch_rq_grant(i)(0) <= switch_rq(lr_vc);
end generate;
GEN_RR : if vc_num_vec(i) > 1 generate
rr_arbiter : entity work.rr_arbiter_no_delay
generic map (
CNT => vc_num_vec(i))
port map (
clk => clk,
rst => rst,
req => switch_rq(ur_vc downto lr_vc),
ack => switch_ack(i),
grant => switch_rq_grant(i)(vc_num_vec(i)-1 downto 0));
end generate;
end generate;
-------------------------------------------------------------------------------
-- Wiring of granted switch request to the according outputs in the order the
-- crossbar select is defined (clock-wise / modulo). Thereby we exploits that
-- some request are not possible, since a routing forbids it for dead and live-
-- lock avoidance (don't care to reduce the circuit complexity after synthesis)
-------------------------------------------------------------------------------
WIRING : process(switch_rq_grant)
variable var_in : natural;
begin
poss_channel_rq <= (others => (others => (others => '-')));
for y in 0 to port_num-1 loop -- For the phy channel at output y,
for x in 0 to port_num-2 loop -- the x^th possible input is
if y+x < port_num-1 then
var_in := y+x+1; -- clock wise
else
var_in := y+x-port_num+1; -- modulo
end if;
if poss_routes(port_exist(var_in))(port_exist(y)) then
poss_channel_rq(y)(x) <= switch_rq_grant(var_in);
end if;
end loop;
end loop;
end process;
-------------------------------------------------------------------------------
-- Choose (multiplex) the "channel_rq" out of the "poss_channel_rq" in depend.
-- of VC allocation ("crossbar_ctrl_vec" & "vc_sel_enc_vec") ------------------
-------------------------------------------------------------------------------
MUX_CHANNEL_RQ_GEN : process(credit_avail, crossbar_ctrl_vc_out, output_vc_in_use,
poss_channel_rq, vc_sel_enc_vec)
variable assigned_input : std_logic_vector(sel_width-1 downto 0);
variable assigned_vc : vc_status_vec_enc;
variable lr_vc_out, ur_vc_out : natural range 0 to int_vec_sum(vc_num_out_vec)-1;
begin
for port_i in 0 to port_num-1 loop
lr_vc_out := lower_range(vc_num_out_vec, port_i);
ur_vc_out := upper_range(vc_num_out_vec, port_i);
for vc_i in lr_vc_out to ur_vc_out loop
assigned_input := crossbar_ctrl_vc_out(vc_i);
assigned_vc := vc_sel_enc_vec(vc_i);
channel_rq(vc_i) <=
poss_channel_rq(port_i)(slv2int(assigned_input))(slv2int(assigned_vc))
and output_vc_in_use(vc_i) and credit_avail(vc_i);
end loop;
end loop;
end process;
-------------------------------------------------------------------------------
-- Generate the physical channel (output) arbiters ----------------------------
-------------------------------------------------------------------------------
OUTPUT_ARB_GEN : for i in 0 to port_num-1 generate
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
begin
PASS_NO_VC : if vc_num_out_vec(i) = 1 generate -- single vc --> no arb. required
channel_grant(lr_vc_out) <= channel_rq(lr_vc_out);
end generate;
-- DESIGNER_HINT maybe use a delayed rr_arbitter (allows speed improvement)
GEN_RR : if vc_num_out_vec(i) > 1 generate
rr_arbiter : entity work.rr_arbiter_no_delay
generic map (
CNT => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
req => channel_rq(ur_vc_out downto lr_vc_out),
ack => '1',
grant => channel_grant(ur_vc_out downto lr_vc_out));
end generate;
CREDIT_COUNT_GENERATE : for vc_i in lr_vc_out to ur_vc_out generate
credit_count_i : entity work.credit_count_single
generic map (
vc_depth_out => vc_depth_out_array(i)(vc_i-lr_vc_out))
port map (
clk => clk,
rst => rst,
incr_rx => incr_rx_vec(vc_i),
vc_write_tx => channel_grant(vc_i), -- EQUAL: vc_write_tx_vec
credit_avail => credit_avail(vc_i));
end generate;
end generate;
vc_write_tx_vec <= channel_grant;
-----------------------------------------------------------------------------
-- Crossbar ctrl, input acknowledge out of winner----------------------------
-----------------------------------------------------------------------------
DECODE_INPUT_ACK : for i in 0 to port_num-1 generate
constant ur : natural := upper_range(vc_num_out_vec, i);
constant lr : natural := lower_range(vc_num_out_vec, i);
begin
process(channel_grant(ur downto lr), crossbar_ctrl_vc_out)
variable winner : natural range 0 to int_vec_sum(vc_num_out_vec)-1;
variable input_winner : natural range 0 to port_num-1;
begin
crossbar_ctrl((i+1)*sel_width-1 downto i*sel_width) <= (others => '-');
switch_acks(i) <= (others => '0');
if vc_num_out_vec(i) = 1 then
winner := lr;
else
winner := lr + one_hot2int(channel_grant(ur downto lr));
end if;
crossbar_ctrl((i+1)*sel_width-1 downto i*sel_width) <= crossbar_ctrl_vc_out(winner);
if or_reduce(channel_grant(ur downto lr)) = '1' then
input_winner := (slv2int(crossbar_ctrl_vc_out(winner))+ i + 1) mod port_num;
switch_acks(i)(input_winner) <= '1';
end if;
end process;
end generate;
INP_ACK : process(switch_acks)
variable switch_ack_var : std_logic_vector(port_num-1 downto 0);
begin
switch_ack_var := (others => '0');
for i in 0 to port_num-1 loop
switch_ack_var := switch_ack_var or switch_acks(i);
end loop;
switch_ack <= switch_ack_var;
end process;
process(switch_ack, switch_rq_grant)
variable ur, lr : natural range 0 to int_vec_sum(vc_num_vec)-1;
begin
vc_transfer_vec_int <= (others => '0');
for i in 0 to port_num-1 loop
if switch_ack(i) = '1' then
ur := upper_range(vc_num_vec, i);
lr := lower_range(vc_num_vec, i);
vc_transfer_vec_int(ur downto lr) <= switch_rq_grant(i)(vc_num_vec(i)-1 downto 0);
end if;
end loop;
end process;
vc_transfer_vec <= vc_transfer_vec_int;
end architecture;

177
noc_files/traffic_corr_tb.vhd Normal file
View file

@ -0,0 +1,177 @@
-------------------------------------------------------------------------------
-- Title : Test pattern receiver
-- Project : NoC testbench generator
-------------------------------------------------------------------------------
-- File : traffic_corr_tb.vhd
-- Author : Seyed Nima Omidsajedi <nima@omidsajedi.com>
-- Company : University of Bremen
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Vesion : 1.7.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.NOC_3D_PACKAGE.all;
entity traffic_corr_tb is
end entity;
architecture behave of traffic_corr_tb is
constant cnt_flit_width : positive := flit_size;
constant cnt_router_credit : integer := 4;
constant cnt_srl_fifo_depth : integer := 8;
constant cnt_rec_time_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_receive_destnode/receive_time_noc.txt";
constant cnt_rec_data_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_receive_destnode/receive_data_noc.txt";
constant cnt_inj_time_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_send_sourcenode/injection_time.txt";
constant cnt_packet_length_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_send_sourcenode/packet_header_length.txt";
constant cnt_image_2_flits_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_send_sourcenode/data_header.txt";
constant cnt_inj_time_2_noc_text : string := "D:/project_item_ids/Noc_files/0_networks_on_chip/0_networks_on_chip/single_routing/python/data_receive_destnode/inj_time_2_noc.txt";
-- constant cnt_rec_time_text : string := "../python/data_receive_destnode/receive_time_noc.txt";
-- constant cnt_rec_data_text : string := "../python/data_receive_destnode/receive_data_noc.txt";
-- constant cnt_inj_time_text : string := "../python/data_send_sourcenode/injection_time.txt";
-- constant cnt_packet_length_text : string := "../python/data_send_sourcenode/packet_header_length.txt";
-- constant cnt_image_2_flits_text : string := "../python/data_send_sourcenode/data_header.txt";
-- constant cnt_inj_time_2_noc_text : string := "../python/data_receive_destnode/inj_time_2_noc.txt";
-------------------------------------------------------------------
signal clk : std_logic := '0';
signal rst : std_logic := RST_LVL;
signal local_rx : flit_vector(48-1 downto 0) := (others => (others => '0'));
signal local_vc_write_rx: std_logic_vector(192-1 downto 0) := (others => '0');
signal local_incr_rx_vec: std_logic_vector(192-1 downto 0) := (others => '0');
signal local_tx : flit_vector(48-1 downto 0);
signal local_vc_write_tx : std_logic_vector(192-1 downto 0);
signal local_incr_tx_vec : std_logic_vector(192-1 downto 0);
-------------------------------------------------------------------
--------------------- Component declaration -----------------------
-- Traffic Receiver
component traffic_rec is
generic(
flit_width : positive := cnt_flit_width;
rec_time_text : string := cnt_rec_time_text;
rec_data_text : string := cnt_rec_data_text
);
port(
clk, rst: in std_logic;
valid: in std_logic;
incr: out std_logic;
data_in: in flit := (others => '0')
);
end component traffic_rec;
-- NoC
component full_noc is
port(
clk, rst : in std_logic;
local_rx : in flit_vector(48-1 downto 0);
local_vc_write_rx : in std_logic_vector(192-1 downto 0);
local_incr_rx_vec : in std_logic_vector(192-1 downto 0);
local_tx : out flit_vector(48-1 downto 0);
local_vc_write_tx : out std_logic_vector(192-1 downto 0);
local_incr_tx_vec : out std_logic_vector(192-1 downto 0)
);
end component full_noc;
-- Traffic Generator
component traffic_gen is
generic(
flit_width : positive := cnt_flit_width;
router_credit : integer := cnt_router_credit;
srl_fifo_depth : integer := cnt_srl_fifo_depth;
inj_time_text : string := cnt_inj_time_text;
packet_length_text : string := cnt_packet_length_text;
image_2_flits_text : string := cnt_image_2_flits_text;
inj_time_2_noc_text : string := cnt_inj_time_2_noc_text
);
port(
clk, rst : in std_logic;
valid : out std_logic;
incr : in std_logic;
data_out : out flit
);
end component traffic_gen;
begin
-------------------------------------------------------------------
------------------- Component instantiations ----------------------
traffic_gen_comp_1: entity work.traffic_gen
generic map(
flit_width => cnt_flit_width,
router_credit => cnt_router_credit,
srl_fifo_depth => cnt_srl_fifo_depth,
inj_time_text => cnt_inj_time_text,
packet_length_text => cnt_packet_length_text,
image_2_flits_text => cnt_image_2_flits_text,
inj_time_2_noc_text => cnt_inj_time_2_noc_text
)
port map(
clk => clk,
rst => rst,
valid => local_vc_write_rx(36),--36 --in [NoC]
incr => local_incr_tx_vec(44),--36 even it is zero value is transmited
data_out => local_rx(9)
);
full_noc_comp: entity work.full_noc
port map(
clk => clk,
rst => rst,
local_rx => local_rx,
local_vc_write_rx => local_vc_write_rx,
local_incr_rx_vec => local_incr_rx_vec,
local_tx => local_tx,
local_vc_write_tx => local_vc_write_tx,
local_incr_tx_vec => local_incr_tx_vec
);
traffic_rec_comp_1: entity work.traffic_rec
generic map(
flit_width => cnt_flit_width,
rec_time_text => cnt_rec_time_text,
rec_data_text => cnt_rec_data_text
)
port map(
clk => clk,
rst => rst,
valid => local_vc_write_tx(4), --out[Noc]
incr => local_incr_rx_vec(4),
data_in => local_tx(1)
);
-------------------------------------------------------------------
----------------------RST & CLK generation-------------------------
rst_gen: process
begin
rst <= RST_LVL;
wait for (clk_period * 2);
rst <= not(RST_LVL);
wait;
end process;
clk_gen:process
begin
clk <= '1';
wait for (clk_period / 2);
clk <= '0';
wait for (clk_period / 2);
end process;
--------------------------------------------------------------------
-------------------------------------------------------------------
end architecture;

201
noc_files/traffic_gen.vhd Normal file
View file

@ -0,0 +1,201 @@
-------------------------------------------------------------------------------
-- Title : Test pattern generator
-- Project : NoC testbench generator
-------------------------------------------------------------------------------
-- File : traffic_gen.vhd
-- Author : Seyed Nima Omidsajedi <nima@omidsajedi.com>
-- Company : University of Bremen
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Vesion : 1.9.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.NOC_3D_PACKAGE.all;
entity traffic_gen is
generic(
flit_width : positive := flit_size;
router_credit : integer := 4;
srl_fifo_depth : integer := 8;
inj_time_text : string := "injection_time.txt";
packet_length_text : string := "packet_length.txt";
image_2_flits_text : string := "data_header.txt";
inj_time_2_noc_text : string := "inj_time_2_noc.txt"
);
port(
clk, rst: in std_logic := '0';
valid: out std_logic := '0';
incr: in std_logic := '0';
data_out: out flit := (others => '0')
);
end entity;
architecture behave of traffic_gen is
component srl_fifo is
generic ( buffer_depth : integer := srl_fifo_depth );
port(
data_in : in flit;
data_out : out flit;
rst : in std_logic;
write_en : in std_logic;
read_en : in std_logic;
buffer_full : out std_logic;
buffer_empty : out std_logic;
clk : in std_logic
);
end component;
signal data_in : flit := (others => '0');
signal data_out_rsl_fifo : flit;
signal credit: integer := router_credit;
signal valid_signal : std_logic := '0';
signal temp_inj_time : natural;
signal temp_packet_length : natural := 0;
signal counter: natural := 0;
signal write_en : std_logic := '0';
signal buffer_full : std_logic := '0';
signal buffer_empty : std_logic := '1';
-- Used text files
file inj_time : text open read_mode is inj_time_text;
file packet_length : text open read_mode is packet_length_text;
file image_2_flits : text open read_mode is image_2_flits_text;
file inj_time_2_noc : text open write_mode is inj_time_2_noc_text;
begin
-------------------------------------------------------------------
------------------ internal buffer component ----------------------
int_buffer: entity work.srl_fifo
generic map ( buffer_depth => srl_fifo_depth)
port map (
data_in => data_in,
data_out => data_out_rsl_fifo,
rst => rst,
write_en => write_en,
read_en => valid_signal,
buffer_full => buffer_full,
buffer_empty => buffer_empty,
clk => clk);
-------------------------------------------------------------------
----------- Read text files into the internal buffer --------------
read_packet_length: process
variable input_line : line;
variable next_data_packet_length: natural;
variable next_inj_time: natural;
variable next_data_flit: flit;
begin
wait until ((rst = not(RST_LVL)) and rising_edge(clk)); -- set reset for design
while not (endfile(packet_length)) loop
write_en <= '0';
readline(packet_length, input_line);
read(input_line, next_data_packet_length);
temp_packet_length <= next_data_packet_length;
readline(inj_time, input_line);
read(input_line, next_inj_time);
temp_inj_time <= next_inj_time;
wait until (counter = temp_inj_time - 1) and rising_edge(clk);
-- Send Data into internal Buffer
for i in 0 to (temp_packet_length - 1) loop
readline(image_2_flits, input_line);
read(input_line, next_data_flit);
data_in <= next_data_flit;
write_en <= '1';
wait until rising_edge(clk);
end loop;
end loop;
-- Put zeros after the whole message tranmission
if endfile(packet_length) then
write_en <= '0';
data_in <= (others => '0');
end if;
end process;
-------------------------------------------------------------------
------------------------- Clk counter -----------------------------
clk_counter: process(clk)
begin
if (rising_edge(clk)) then
if (rst = RST_LVL) then
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
-------------------------------------------------------------------
------------------------ Credit counter ---------------------------
credit_counter: process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = RST_LVL) then
credit <= router_credit ;
else
if ((credit > 0) and valid_signal = '1' and incr = '0') then
credit <= credit - 1;
elsif ((credit < router_credit) and valid_signal = '0') then
credit <= credit + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
---------------------- Determine valid flag -----------------------
data_out <= data_out_rsl_fifo;
valid_flag: process(buffer_empty, credit, incr)
begin
if ( buffer_empty = '0' and (( credit > 0) or (incr = '1'))) then
valid <= '1';
valid_signal <= '1';
else
valid <= '0';
valid_signal <= '0';
end if;
end process;
-------------------------------------------------------------------
------------------- Save injection time to NoC --------------------
write_inj_time: process(clk, rst)
variable rowOut: line;
variable data_time: time := 0 ns;
begin
if clk = '1' and clk'event and rst = not(RST_LVL) then
if (valid_signal = '1') then
data_time := now - clk_period;
write(rowOut, data_time);
writeline(inj_time_2_noc, rowOut);
end if;
end if;
end process;
--------------------------------------------------------------------
-------------------------------------------------------------------
end architecture;

67
noc_files/traffic_rec.vhd Normal file
View file

@ -0,0 +1,67 @@
-------------------------------------------------------------------------------
-- Title : Test pattern receiver
-- Project : NoC testbench generator
-------------------------------------------------------------------------------
-- File : traffic_rec.vhd
-- Author : Seyed Nima Omidsajedi <nima@omidsajedi.com>
-- Company : University of Bremen
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Vesion : 1.9.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.NOC_3D_PACKAGE.all;
entity traffic_rec is
generic(
flit_width : positive := flit_size;
rec_time_text : string := "receive_time_noc.txt";
rec_data_text : string := "receive_data_noc.txt"
);
port(
clk, rst : in std_logic := '0';
valid : in std_logic := '0';
incr : out std_logic := '0';
data_in : in flit := (others => '0')
);
end entity;
architecture behave of traffic_rec is
-- Used text files
file rec_time : text open write_mode is rec_time_text;
file rec_data : text open write_mode is rec_data_text;
begin
-- Set increment
incr <= valid;
-------------------------------------------------------------------
--------------------------- write Process -------------------------
write_data: process(clk, rst)
variable rowOut: line;
variable data_time: time := 0 ns;
begin
if clk = '1' and clk'event and rst = not(RST_LVL) then
if (valid = '1') then
write(rowOut, data_in);
writeline(rec_data, rowOut);
data_time := now - clk_period;
write(rowOut, data_time);
writeline(rec_time, rowOut);
end if;
end if;
end process;
--------------------------------------------------------------------
-------------------------------------------------------------------
end architecture;

67
noc_files/uxyd_routing.vhd Normal file
View file

@ -0,0 +1,67 @@
-------------------------------------------------------------------------------
-- Title : Up-X-Y-Down routing for a router at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : uxyd_routing.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity uxyd_routing is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end uxyd_routing;
architecture rtl of uxyd_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.z_dest)) > Zis) then
routing(int_down) <= '1'; -- Route pos. Z
elsif (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
elsif (to_integer(unsigned(address.z_dest)) < Zis) then
routing(int_up) <= '1'; -- Route neg. Z
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;

160
noc_files/vc_allocator.vhd Normal file
View file

@ -0,0 +1,160 @@
-------------------------------------------------------------------------------
-- Title : Virtual channel allocator
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_allocator.vhd
-- Author : Lennart Bamberg <lennart@t440s>
-- Company :
-- Created : 2018-11-11
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: New package are detected in an input port, then the required
-- informations (routing & packet length) are decoded from the
-- header. Finally, a suitable output virtual channel is assigned.
-- COMMENT:
-- Currently, this version is not used (but the high perf. one)!
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-11 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
use work.TURNS_3D_NOC.all;
entity vc_allocator is
generic (
port_num : positive := 7;
-- Integer range has to be / is (0 to port_num-1)
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
rout_algo : string := "DXYU";
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 ));
port (
clk, rst : in std_logic;
header : in header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
enr_vc : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
input_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
crossbar_ctrl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)*
bit_width(port_num-1)-1 downto 0);
vc_sel_enc_vec : out vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
output_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0)
);
end entity vc_allocator;
architecture rtl of vc_allocator is
constant poss_routes : turn_table_3D := routes_3D(rout_algo);
constant sel_width : positive := bit_width(port_num-1);
signal ack_input : std_logic_vector(port_num-1 downto 0);
signal packet_end : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
type rq_array is array (port_num-1 downto 0) of std_logic_vector(port_num-1 downto 0);
type rq_array_filt is array (port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
signal granted_rq_array : rq_array;
signal rq_vc_out_array : rq_array_filt;
type vc_status_array_filt is array (port_num-1 downto 0) of vc_status_array(port_num-2 downto 0);
signal packet_end_sort : vc_status_array_filt;
signal granted_vc_sort : vc_status_array_filt;
signal granted_vc : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
type ack_array_vc_out is array(port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
signal ack_rq_vc_out : ack_array_vc_out;
begin -- architecture rtl
GEN_PER_PORT : for i in 0 to port_num-1 generate
constant ur_vc_in : natural := upper_range(vc_num_vec, i);
constant lr_vc_in : natural := lower_range(vc_num_vec, i);
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
begin
---------------------------------------------------------------------------
-- Header decoder and input arbiter per port-------------------------------
---------------------------------------------------------------------------
input_first_arbiter_i : entity work.header_arbiter_and_decoder
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis,
port_num => port_num,
port_exist => port_exist,
port_is => port_exist(i),
vc_num => vc_num_vec(i),
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo)
port map (
clk => clk,
rst => rst,
valid_data_vc => valid_data_vc_vec(ur_vc_in downto lr_vc_in),
header => header(ur_vc_in downto lr_vc_in),
enr_vc => enr_vc(ur_vc_in downto lr_vc_in),
ack_vc => ack_input(i),
granted_rq => granted_rq_array(i),
input_vc_in_use => input_vc_in_use(ur_vc_in downto lr_vc_in),
packet_end => packet_end(ur_vc_in downto lr_vc_in),
granted_vc => granted_vc(ur_vc_in downto lr_vc_in));
---------------------------------------------------------------------------
-- Output VC arbiter/allocator per port -----------------------------------
---------------------------------------------------------------------------
output_last_arbiter_i : entity work.vc_output_allocator
generic map (
port_num => port_num,
vc_num_out => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
rq_vc_out => rq_vc_out_array(i),
granted_vc => granted_vc_sort(i),
packet_end => packet_end_sort(i),
crossbar_ctrl_vec => crossbar_ctrl_vec((ur_vc_out+1)*sel_width-1 downto lr_vc_out*sel_width),
vc_sel_enc => vc_sel_enc_vec(ur_vc_out downto lr_vc_out),
output_vc_in_use => output_vc_in_use(ur_vc_out downto lr_vc_out),
ack_rq_vc_out => ack_rq_vc_out(i)
);
end generate;
-----------------------------------------------------------------------------
-- Clock Wise Wiring --------------------------------------------------------
-----------------------------------------------------------------------------
WIRING_INAR_TO_OUTAR : process(ack_rq_vc_out, granted_rq_array, granted_vc,
packet_end)
variable var_in : natural;
variable ack_rq_vc_out_var : std_logic_vector(port_num-1 downto 0);
begin
rq_vc_out_array <= (others => (others => '0'));
granted_vc_sort <= (others => (others => (others => '0')));
packet_end_sort <= (others => (others => (others => '0')));
ack_rq_vc_out_var := (others => '0');
for y in 0 to port_num-1 loop -- For the VC-out allocator y,
for x in 0 to port_num-2 loop -- the X^th input is
if y+x < port_num-1 then
var_in := y+x+1;
else -- Modulo (start from beginning)
var_in := y+x-port_num+1;
end if;
if poss_routes(port_exist(var_in))(port_exist(y)) then
rq_vc_out_array(y)(x) <= granted_rq_array(var_in)(y);
granted_vc_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
<= slice(granted_vc, vc_num_vec, var_in);
packet_end_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
<= slice(packet_end, vc_num_vec, var_in);
ack_rq_vc_out_var(var_in) := ack_rq_vc_out_var(var_in) or
ack_rq_vc_out(y)(x); --feedback ack
end if;
end loop;
end loop;
ack_input <= ack_rq_vc_out_var;
end process;
end architecture rtl;

162
noc_files/vc_allocator_high_perf.vhd Normal file
View file

@ -0,0 +1,162 @@
-------------------------------------------------------------------------------
-- Title : Virtual channel allocator with an extension to increase the
-- network performance.
-- The higher network performance compared to the baseline is gi-
-- ven by removing the clock cycle where a VC is unused until the
-- the next one is assigned. The drawback is a higher complexity.
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_allocator_high_perf.vhd
-- Author : Lennart Bamberg <lennart@t440s>
-- Company :
-- Created : 2018-11-11
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: New package are detected in an input port, then the required
-- informations (routing & packet length) are decoded from the
-- header. Finally, a suitable output virtual channel is assigned.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-11 1.0 lennart Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
use work.TURNS_3D_NOC.all;
entity vc_allocator_high_perf is
generic (
port_num : positive := 7;
-- Integer range has to be / is (0 to port_num-1)
port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1;
header_incl_in_packet_length : boolean := true;
rout_algo : string := "DXYU";
vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 ));
port (
clk, rst : in std_logic;
header : in header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
enr_vc : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
input_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
crossbar_ctrl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)*
bit_width(port_num-1)-1 downto 0);
vc_sel_enc_vec : out vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
output_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0)
);
end entity vc_allocator_high_perf;
architecture rtl of vc_allocator_high_perf is
constant poss_routes : turn_table_3D := routes_3D(rout_algo);
constant sel_width : positive := bit_width(port_num-1);
signal ack_input : std_logic_vector(port_num-1 downto 0);
signal packet_end : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
type rq_array is array (port_num-1 downto 0) of std_logic_vector(port_num-1 downto 0);
type rq_array_filt is array (port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
signal granted_rq_array : rq_array;
signal rq_vc_out_array : rq_array_filt;
type vc_status_array_filt is array (port_num-1 downto 0) of vc_status_array(port_num-2 downto 0);
signal packet_end_sort : vc_status_array_filt;
signal granted_vc_sort : vc_status_array_filt;
signal granted_vc : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
type ack_array_vc_out is array(port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
signal ack_rq_vc_out : ack_array_vc_out;
begin -- architecture rtl
GEN_PER_PORT : for i in 0 to port_num-1 generate
constant ur_vc_in : natural := upper_range(vc_num_vec, i);
constant lr_vc_in : natural := lower_range(vc_num_vec, i);
constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
begin
---------------------------------------------------------------------------
-- Header decoder and input arbiter per port-------------------------------
---------------------------------------------------------------------------
input_first_arbiter_i : entity work.header_arbiter_and_decoder
generic map (
Xis => Xis,
Yis => Yis,
Zis => Zis,
port_num => port_num,
port_exist => port_exist,
port_is => port_exist(i),
vc_num => vc_num_vec(i),
header_incl_in_packet_length => header_incl_in_packet_length,
rout_algo => rout_algo)
port map (
clk => clk,
rst => rst,
valid_data_vc => valid_data_vc_vec(ur_vc_in downto lr_vc_in),
header => header(ur_vc_in downto lr_vc_in),
enr_vc => enr_vc(ur_vc_in downto lr_vc_in),
ack_vc => ack_input(i),
granted_rq => granted_rq_array(i),
input_vc_in_use => input_vc_in_use(ur_vc_in downto lr_vc_in),
packet_end => packet_end(ur_vc_in downto lr_vc_in),
granted_vc => granted_vc(ur_vc_in downto lr_vc_in));
---------------------------------------------------------------------------
-- Output VC arbiter/allocator per port -----------------------------------
---------------------------------------------------------------------------
output_last_arbiter_i : entity work.vc_output_allocator_high_perf
generic map (
port_num => port_num,
vc_num_out => vc_num_out_vec(i))
port map (
clk => clk,
rst => rst,
rq_vc_out => rq_vc_out_array(i),
granted_vc => granted_vc_sort(i),
packet_end => packet_end_sort(i),
crossbar_ctrl_vec => crossbar_ctrl_vec((ur_vc_out+1)*sel_width-1 downto lr_vc_out*sel_width),
vc_sel_enc => vc_sel_enc_vec(ur_vc_out downto lr_vc_out),
output_vc_in_use => output_vc_in_use(ur_vc_out downto lr_vc_out),
ack_rq_vc_out => ack_rq_vc_out(i)
);
end generate;
-----------------------------------------------------------------------------
-- Clock Wise Wiring --------------------------------------------------------
-----------------------------------------------------------------------------
WIRING_INAR_TO_OUTAR : process(ack_rq_vc_out, granted_rq_array, granted_vc,
packet_end)
variable var_in : natural;
variable ack_rq_vc_out_var : std_logic_vector(port_num-1 downto 0);
begin
rq_vc_out_array <= (others => (others => '0'));
granted_vc_sort <= (others => (others => (others => '0')));
packet_end_sort <= (others => (others => (others => '0')));
ack_rq_vc_out_var := (others => '0');
for y in 0 to port_num-1 loop -- For the VC-out allocator y,
for x in 0 to port_num-2 loop -- the X^th input is
if y+x < port_num-1 then
var_in := y+x+1;
else -- Modulo (start from beginning)
var_in := y+x-port_num+1;
end if;
if poss_routes(port_exist(var_in))(port_exist(y)) then
rq_vc_out_array(y)(x) <= granted_rq_array(var_in)(y);
granted_vc_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
<= slice(granted_vc, vc_num_vec, var_in);
packet_end_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
<= slice(packet_end, vc_num_vec, var_in);
ack_rq_vc_out_var(var_in) := ack_rq_vc_out_var(var_in) or
ack_rq_vc_out(y)(x); --feedback ack
end if;
end loop;
end loop;
ack_input <= ack_rq_vc_out_var;
end process;
end architecture rtl;

99
noc_files/vc_input_buffer.vhd Normal file
View file

@ -0,0 +1,99 @@
-------------------------------------------------------------------------------
-- Title : Input buffer when virtual channels are used
-- (for credit based flow-control)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_input_buffer.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-05-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: An input buffer consists of vc_num (number of virtual channels)
-- paralell input buffers, whose depth is defined via "vc_depth".
-- The one hot encoded signal vc_write_rx determines in which VC
-- data is written (max. 1). vc_transfer determines from which VC
-- data is transfered to the next router (max. 1).
-- The LSBs of the next flit are forwarded to the the centralized
-- arbiter, as they containing the information req. to route the
-- package of the network if the flit is a head-flit. Also the
-- information which VC contains valid data is provided for the
-- centralized arbiter.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-05-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
entity vc_input_buffer is
generic(vc_num : positive := 4; -- Virtual channels (VC)
vc_depth : integer_vec := (4 ,4 ,4 ,4 )); -- Buff depth of each VC
port(clk : in std_logic;
rst : in std_logic;
data_rx : in flit;
vc_write_rx : in std_logic_vector(vc_num-1 downto 0); -- Write EN VC
vc_transfer : in std_logic_vector(vc_num-1 downto 0); -- Read EN VC
valid_data_vc : out std_logic_vector(vc_num-1 downto 0); --
data_transfer : out flit; --
-- Information from the header that are required for path-finding
-- and channel allocation (Destination Address & Packet-Length)
header : out header_inf_vector(vc_num-1 downto 0)
);
end entity vc_input_buffer;
architecture rtl of vc_input_buffer is
signal buffer_out_vector : flit_vector(vc_num-1 downto 0);
begin
-----------------------------------------------------------------------------
------------- Structural Part - Generate FIFOs for each VC ------------------
-----------------------------------------------------------------------------
buffer_gen : for i in 0 to vc_num-1 generate
fifo_i : entity work.fifo generic map(buff_depth => vc_depth(vc_depth'left+i))
port map (data_in => data_rx,
write_en => vc_write_rx(i),
read_en => vc_transfer(i),
clk => clk,
rst => rst,
data_out => buffer_out_vector(i),
valid_data => valid_data_vc(i)
);
end generate buffer_gen;
-----------------------------------------------------------------------------
------------- Logic Part - Calculate outputs --------------------------------
-----------------------------------------------------------------------------
OUTPUT_MUX : if vc_num > 1 generate
process(buffer_out_vector, vc_transfer)
begin
data_transfer <= (others => '-');
if or_reduce(vc_transfer) = '1' then
data_transfer <= buffer_out_vector(one_hot2int(vc_transfer));
end if;
end process;
end generate;
OUTPUT_PASS : if vc_num = 1 generate
data_transfer <= buffer_out_vector(0);
end generate;
HEADER_GEN : for i in 0 to vc_num-1 generate
header(i) <= get_header_inf(buffer_out_vector(i));
end generate;
end rtl;

102
noc_files/vc_input_buffer_enc_sel.vhd Normal file
View file

@ -0,0 +1,102 @@
-------------------------------------------------------------------------------
-- Title : Input buffer when virtual channels are used
-- (for credit based flow-control)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_input_buffer_enc_sel.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-05-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Reasonable only for more than four VCs (=> NOT USED CURRENTLY!)
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-05-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.NOC_3D_PACKAGE.all;
entity vc_input_buffer_enc_sel is
generic(vc_num : positive := 4; -- Virtual channels (VC)
vc_depth : integer_vec := (4 ,4 ,4 ,4 )); -- Array including the buffer
-- depths of each VC
port(clk : in std_logic;
rst : in std_logic;
data_rx : in flit;
-- "sel" signal to determine in which VC "data_rx" is written
vc_sel_write_rx : in std_logic_vector(bit_width(vc_num)-1 downto 0); --
-- "sel" signal to determine from which VC "data_rx" is read
vc_sel_transfer : in std_logic_vector(bit_width(vc_num)-1 downto 0); --
-- Indicate if "data_rx" is valid new data
valid_rx : in std_logic; --
-- Indicate if a flit from the input buffer can be transfered
transfer : in std_logic; --
-- Indicate which VC contains valid data
valid_data_vc : out std_logic_vector(vc_num-1 downto 0); --
data_transfer : out flit; --
-- Credit counter increment signals (One Hot)
incr_tx : out std_logic_vector(vc_num-1 downto 0);
-- Information from the header that are required for path-finding
-- and channel allocation (Destination Address & Packet-Length)
header : out header_inf_vector(vc_num-1 downto 0)
);
end entity vc_input_buffer_enc_sel;
architecture rtl of vc_input_buffer_enc_sel is
-- ENR_VC, ENW_VC AND INCR_TX ARE ONE_HOT ENCODED (all zeros also poss)
signal enr_vc : std_logic_vector(vc_num-1 downto 0);
signal enw_vc : std_logic_vector(vc_num-1 downto 0);
signal buffer_out_vector : flit_vector(vc_num-1 downto 0);
begin
-- Structural Part - Generate FIFOs for each VC
buffer_gen : for i in 0 to vc_num-1 generate
fifo_i : entity work.fifo generic map(buff_depth => vc_depth(vc_depth'left+i))
port map (data_in => data_rx,
write_en => enw_vc(i),
read_en => enr_vc(i),
clk => clk,
rst => rst,
data_out => buffer_out_vector(i),
valid_data => valid_data_vc(i)
);
end generate buffer_gen;
-- Geneate "Write-Enable" signals
process(vc_sel_write_rx, valid_rx)
begin
enw_vc <= (others => '0');
enw_vc(slv2int(vc_sel_write_rx)) <= valid_rx;
end process;
-- Geneate "Read-Enable" signals (equal incr_txement hear)
process(transfer, vc_sel_write_rx)
begin
enr_vc <= (others => '0');
enr_vc(slv2int(vc_sel_write_rx)) <= transfer;
end process;
incr_tx <= enr_vc;
-- Generate "data_out"
data_transfer <= buffer_out_vector(slv2int(vc_sel_transfer));
HEADER_GEN : for i in 0 to vc_num-1 generate
header(i) <= get_header_inf(buffer_out_vector(i));
end generate;
end rtl;

128
noc_files/vc_output_allocator.vhd Normal file
View file

@ -0,0 +1,128 @@
-------------------------------------------------------------------------------
-- Title : Allocation of output VCs of a port in a prioroty manner (VC0 first)
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_output_allocator.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-11-09
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-09 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
entity vc_output_allocator is
generic (
port_num : positive := 7;
vc_num_out : positive := 4);
port (
clk, rst : in std_logic;
rq_vc_out : in std_logic_vector(port_num-2 downto 0);
granted_vc : in vc_status_array(port_num-2 downto 0);
packet_end : in vc_status_array(port_num-2 downto 0);
crossbar_ctrl_vec : out std_logic_vector
(vc_num_out*bit_width(port_num-1)-1 downto 0);
vc_sel_enc : out vc_status_array_enc(vc_num_out-1 downto 0);
output_vc_in_use : out std_logic_vector(vc_num_out-1 downto 0);
ack_rq_vc_out : out std_logic_vector(port_num-2 downto 0));
end entity vc_output_allocator;
architecture rtl of vc_output_allocator is
constant sel_wdth : integer := bit_width(port_num-1);
type crossbar_sel_vec is array(vc_num_out-1 downto 0)
of std_logic_vector(sel_wdth-1 downto 0);
signal crossbar_sels : crossbar_sel_vec;
signal vc_available : std_logic;
signal valid_rq : std_logic;
signal output_vc_in_use_int, free_vc_out, next_vc_out :
std_logic_vector(vc_num_out-1 downto 0);
signal vc_sel_enc_int : vc_status_array_enc(vc_num_out-1 downto 0);
signal grant : std_logic_vector(port_num-2 downto 0);
signal next_sel : std_logic_vector(sel_wdth-1 downto 0);
signal next_vc_in_enc : std_logic_vector(
bit_width(max_vc_num)-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Round robin arbitration between all request ------------------------------
-----------------------------------------------------------------------------
rr_arbiter : entity work.rr_arbiter_no_delay
generic map (
CNT => port_num-1)
port map (
clk => clk,
rst => rst,
req => rq_vc_out,
ack => vc_available,
grant => grant);
-- Extract. information of the winning/next-granted rquest
valid_rq <= or_reduce(grant);
next_sel <= one_hot2slv(grant);
next_vc_in_enc <= one_hot2slv(
granted_vc(one_hot2int(grant)));
-----------------------------------------------------------------------------
-- Register that contain information about all output VCs such as source
-- (Input & VC), and the logic for the register transitions -----------------
-----------------------------------------------------------------------------
STOR_GEN : for i in 0 to vc_num_out-1 generate
begin
crossbar_ctrl_vec((i+1)*sel_wdth-1 downto i*sel_wdth) <= crossbar_sels(i);
-- Reg gen to store the information of the output VC usage
process(clk, rst)
begin
if rst = RST_LVL then
crossbar_sels(i) <= (others => '0');
vc_sel_enc_int(i) <= (others => '0');
elsif rising_edge(clk) then
if (next_vc_out(i) and valid_rq) = '1' then
crossbar_sels(i) <= next_sel;
vc_sel_enc_int(i) <= next_vc_in_enc;
end if;
end if;
end process;
-- 1-bit register to keep the status of the VC
process(clk, rst)
begin
if rst = RST_LVL then
output_vc_in_use_int(i) <= '0';
elsif rising_edge(clk) then
if (next_vc_out(i) and valid_rq) = '1' then
output_vc_in_use_int(i) <= '1';
elsif free_vc_out(i) = '1' then
output_vc_in_use_int(i) <= '0';
end if;
end if;
end process;
-- Signal that checks if an assigned output vc is free again
free_vc_out(i) <= packet_end(slv2int(crossbar_sels(i)))
(slv2int(vc_sel_enc_int(i)));
--free_vc_out(i)<= packet_end(1)(1);
end generate;
-- Isolate LSB of all free/unused output VCs (next assigned VC)
next_vc_out <= not(output_vc_in_use_int) and
std_logic_vector(unsigned(output_vc_in_use_int) + 1);
-----------------------------------------------------------------------------
-- Acknowledge input request the assignment of an output VC-----------------
-----------------------------------------------------------------------------
vc_available <= or_reduce(not(output_vc_in_use_int));
ack_rq_vc_out <= grant when vc_available = '1' else (others => '0');
output_vc_in_use <= output_vc_in_use_int;
vc_sel_enc <= vc_sel_enc_int;
end architecture rtl;

137
noc_files/vc_output_allocator_high_perf.vhd Normal file
View file

@ -0,0 +1,137 @@
-------------------------------------------------------------------------------
-- Title : Allocation of output VCs of a port in a Priority manner (VC0
-- first) with an extension to increase the network performance.
-- The higher network performance compared to the baseline is gi-
-- ven by removing the clock cycle where a VC is unused until the
-- the next one is assigned. The drawback is a higher complexity.
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : vc_output_allocator_high_perf.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company :
-- Created : 2018-11-09
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-11-09 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.NOC_3D_PACKAGE.all;
entity vc_output_allocator_high_perf is
generic (
port_num : positive := 7;
vc_num_out : positive := 4);
port (
clk, rst : in std_logic;
rq_vc_out : in std_logic_vector(port_num-2 downto 0);
granted_vc : in vc_status_array(port_num-2 downto 0);
packet_end : in vc_status_array(port_num-2 downto 0);
crossbar_ctrl_vec : out std_logic_vector
(vc_num_out*bit_width(port_num-1)-1 downto 0);
vc_sel_enc : out vc_status_array_enc(vc_num_out-1 downto 0);
output_vc_in_use : out std_logic_vector(vc_num_out-1 downto 0);
ack_rq_vc_out : out std_logic_vector(port_num-2 downto 0));
end entity vc_output_allocator_high_perf;
architecture rtl of vc_output_allocator_high_perf is
constant sel_wdth : integer := bit_width(port_num-1);
type crossbar_sel_vec is array(vc_num_out-1 downto 0)
of std_logic_vector(sel_wdth-1 downto 0);
signal crossbar_sels : crossbar_sel_vec;
signal vc_available : std_logic;
signal valid_rq : std_logic;
signal output_vc_in_use_int, free_vc_out, next_vc_out, output_vc_available :
std_logic_vector(vc_num_out-1 downto 0);
signal vc_sel_enc_int : vc_status_array_enc(vc_num_out-1 downto 0);
signal grant : std_logic_vector(port_num-2 downto 0);
signal next_sel : std_logic_vector(sel_wdth-1 downto 0);
signal next_vc_in_enc : std_logic_vector(
bit_width(max_vc_num)-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Round robin arbitration between all rquest ------------------------------
-----------------------------------------------------------------------------
rr_arbiter : entity work.rr_arbiter_no_delay
generic map (
CNT => port_num-1)
port map (
clk => clk,
rst => rst,
req => rq_vc_out,
ack => vc_available,
grant => grant);
-- Extract. information of the winning/next-granted rquest
valid_rq <= or_reduce(grant);
next_sel <= one_hot2slv(grant);
next_vc_in_enc <= one_hot2slv(
granted_vc(one_hot2int(grant)));
-----------------------------------------------------------------------------
-- Register that contain information about all output VCs such as source
-- (Input & VC), and the logic for the register transitions -----------------
-----------------------------------------------------------------------------
STOR_GEN : for i in 0 to vc_num_out-1 generate
begin
crossbar_ctrl_vec((i+1)*sel_wdth-1 downto i*sel_wdth) <= crossbar_sels(i);
-- Reg gen to store the information of the output VC usage
process(clk, rst)
begin
if rst = RST_LVL then
crossbar_sels(i) <= (others => '0');
vc_sel_enc_int(i) <= (others => '0');
elsif rising_edge(clk) then
if (next_vc_out(i) and valid_rq) = '1' then
crossbar_sels(i) <= next_sel;
vc_sel_enc_int(i) <= next_vc_in_enc;
end if;
end if;
end process;
-- 1-bit register to keep the status of the VC
process(clk, rst)
begin
if rst = RST_LVL then
output_vc_in_use_int(i) <= '0';
elsif rising_edge(clk) then
if (next_vc_out(i) and valid_rq) = '1' then
output_vc_in_use_int(i) <= '1';
elsif free_vc_out(i) = '1' then
output_vc_in_use_int(i) <= '0';
end if;
end if;
end process;
-- Signal that checks if an assigned output vc is free again
free_vc_out(i) <= packet_end(slv2int(crossbar_sels(i)))
(slv2int(vc_sel_enc_int(i)));
--free_vc_out(i)<= packet_end(1)(1);
end generate;
-- Isolate LSB of all free/unused output VCs (next assigned VC)
output_vc_available <= free_vc_out or (not(output_vc_in_use_int));
next_vc_out <= output_vc_available and
std_logic_vector(unsigned(not(output_vc_available)) + 1);
-----------------------------------------------------------------------------
-- Acknowledge input request the assignment of an output VC-----------------
-----------------------------------------------------------------------------
vc_available <= or_reduce(output_vc_available);
ack_rq_vc_out <= grant when vc_available = '1' else (others => '0');
output_vc_in_use <= output_vc_in_use_int;
vc_sel_enc <= vc_sel_enc_int;
end architecture rtl;

61
noc_files/xy_routing.vhd Normal file
View file

@ -0,0 +1,61 @@
-------------------------------------------------------------------------------
-- Title : XY-Up routing for a 2D router at position (Xis,Yis) in a
-- 3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : xy_routing.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity xy_routing is
generic(
Xis : natural := 1;
Yis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end xy_routing;
architecture rtl of xy_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;

67
noc_files/xyz_routing.vhd Normal file
View file

@ -0,0 +1,67 @@
-------------------------------------------------------------------------------
-- Title : XYZ routing for a router at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : xyz_routing.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity xyz_routing is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end xyz_routing;
architecture rtl of xyz_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
elsif (to_integer(unsigned(address.z_dest)) < Zis) then
routing(int_down) <= '1'; -- Route Down
elsif (to_integer(unsigned(address.z_dest)) > Zis) then
routing(int_up) <= '1'; -- Route pos. Z
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;

67
noc_files/zxy_routing.vhd Normal file
View file

@ -0,0 +1,67 @@
-------------------------------------------------------------------------------
-- Title : ZXY routing for a router at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : zxy_routing.vhd
-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity zxy_routing is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end zxy_routing;
architecture rtl of zxy_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.z_dest)) < Zis) then
routing(int_down) <= '1'; -- Route Down
elsif (to_integer(unsigned(address.z_dest)) > Zis) then
routing(int_up) <= '1'; -- Route pos. Z
elsif (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;